Code-generation currently misses some opportunities for optimized sequences when zero-extension is combined with shifts.
Philipp Tomsich (3): RISC-V: add consecutive_bits_operand predicate RISC-V: Split slli+sh[123]add.uw opportunities to avoid zext.w RISC-V: Replace zero_extendsidi2_shifted with generalized split gcc/config/riscv/bitmanip.md | 44 ++++++++++++++++++++++ gcc/config/riscv/predicates.md | 11 ++++++ gcc/config/riscv/riscv.md | 37 +++++++++--------- gcc/testsuite/gcc.target/riscv/zba-shadd.c | 13 +++++++ 4 files changed, 88 insertions(+), 17 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shadd.c -- 2.34.1