Using AMOSWAP as atomic store does not allow us to do sub-word accesses.
Further, it is not consistent with our atomic_load () implementation.
The benefit of AMOSWAP is that the resulting code sequence will be
smaller (comapred to FENCE+STORE), however, this does not weight
out for the lack of sub-word accesses.
Additionally, HW implementors have claimed that an optimal
implementation AMOSWAP is slightly more expensive than FENCE+STORE.
So let's use STORE instead of AMOSWAP.
gcc/
PR 100265
* config/riscv/sync.md (atomic_store<mode>):
Remove.
---
gcc/config/riscv/sync.md | 11 -----------
1 file changed, 11 deletions(-)
diff --git a/gcc/config/riscv/sync.md b/gcc/config/riscv/sync.md
index ddaeda0116d..86f4cef6af9 100644
--- a/gcc/config/riscv/sync.md
+++ b/gcc/config/riscv/sync.md
@@ -57,17 +57,6 @@ (define_insn "mem_thread_fence_1"
;; Atomic memory operations.
-;; Implement atomic stores with amoswap. Fall back to fences for atomic loads.
-(define_insn "atomic_store<mode>"
- [(set (match_operand:GPR 0 "memory_operand" "=A")
- (unspec_volatile:GPR
- [(match_operand:GPR 1 "reg_or_0_operand" "rJ")
- (match_operand:SI 2 "const_int_operand")] ;; model
- UNSPEC_ATOMIC_STORE))]
- "TARGET_ATOMIC"
- "amoswap.<amo>%A2 zero,%z1,%0"
- [(set (attr "length") (const_int 8))])
-
(define_insn "atomic_<atomic_optab><mode>"
[(set (match_operand:GPR 0 "memory_operand" "+A")
(unspec_volatile:GPR
--
2.35.3
