On 03/21/2012 01:35 PM, Aldy Hernandez wrote:
In the test below, we cannot cache either [x] or [y] neither before
the load of flag1 nor the load of flag2. This is because the
corresponding store/release can flush a different value of x or y:
+ if (__atomic_load_n (&flag1, __ATOMIC_ACQUIRE))
+ i = x + y;
+ if (__atomic_load_n (&flag2, __ATOMIC_ACQUIRE))
+ a = 10;
+ j = x + y;
Actually, does it need to be that complicated?
can't you simply have the "other_thread" process monotonically increase
x by 1 every cycle?
then if the load is hoisted and commoned,
simulate_thread_final_verify() can simply check that if i == j, it
knows that x was loaded as a common value and reused when calculating
j. with the other thread increasing x eveyr sycle, they should never
be the same value.