On Mon, Jul 4, 2022 at 9:11 PM Roger Sayle <ro...@nextmovesoftware.com> wrote:
>
>
> This patch is the latest revision of the patch originally posted at:
> https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596201.html
>
> This patch extends the earlier and;cmp to not;test optimization to also
> perform this transformation for TImode on TARGET_64BIT and DImode on -m32,
> One motivation for this is that it's a step to fixing the current failure
> of gcc.target/i386/pr65105-5.c on -m32.
>
> A more direct benefit for x86_64 is that the following code:
>
> int foo(__int128 x, __int128 y)
> {
> return (x & y) == y;
> }
>
> improves with -O2 from 15 instructions:
>
> movq %rdi, %r8
> movq %rsi, %rax
> movq %rax, %rdi
> movq %r8, %rsi
> movq %rdx, %r8
> andq %rdx, %rsi
> andq %rcx, %rdi
> movq %rsi, %rax
> movq %rdi, %rdx
> xorq %r8, %rax
> xorq %rcx, %rdx
> orq %rdx, %rax
> sete %al
> movzbl %al, %eax
> ret
>
> to the slightly better 13 instructions:
>
> movq %rdi, %r8
> movq %rsi, %rax
> movq %r8, %rsi
> movq %rax, %rdi
> notq %rsi
> notq %rdi
> andq %rdx, %rsi
> andq %rcx, %rdi
> movq %rsi, %rax
> orq %rdi, %rax
> sete %al
> movzbl %al, %eax
> ret
>
> Now that all of the doubleword pieces are already in the tree, this
> patch is now much shorter (an rtx_costs improvement and a single new
> define_insn_and_split), however I couldn't resist including two very
> minor pattern naming tweaks/clean-ups to fix nits.
>
> This revised patch has been tested on x86_64-pc-linux-gnu with
> make bootstrap and make -k check, where on TARGET_64BIT there are
> no new failures, and on --target_board=unix{-m32} with a single new
> failure; the other dg-final in gcc.target/i386/pr65105-5.c now also
> fails (as that code diverges further from the expected vectorized
> output). This is progress as both FAILs in pr65105-5.c may now be
> fixed by changes localized to the STV pass. OK for mainline?
>
>
> 2022-07-04 Roger Sayle <ro...@nextmovesoftware.com>
>
> gcc/ChangeLog
> * config/i386/i386.cc (ix86_rtx_costs) <COMPARE>: Provide costs
> for double word comparisons and tests (comparisons against zero).
> * config/i386/i386.md (*test<mode>_not_doubleword): Split DWI
> and;cmp into andn;cmp $0 as a pre-reload splitter.
> (*andn<dwi>3_doubleword_bmi): Use <dwi> instead of <mode> in name.
> (*<any_or><dwi>3_doubleword): Likewise.
>
> gcc/testsuite/ChangeLog
> * gcc.target/i386/testnot-3.c: New test case.
>
+;; Split and;cmp (as optimized by combine) into andn;cmp $0
+(define_insn_and_split "*test<mode>_not_doubleword"
+ [(set (reg:CCZ FLAGS_REG)
+ (compare:CCZ
+ (and:DWI
+ (not:DWI (match_operand:DWI 0 "nonimmediate_operand"))
+ (match_operand:DWI 1 "nonimmediate_operand"))
+ (const_int 0)))]
+ "ix86_pre_reload_split ()"
+ "#"
+ "&& 1"
+ [(parallel
+ [(set (match_dup 2) (and:DWI (not:DWI (match_dup 0)) (match_dup 1)))
+ (clobber (reg:CC FLAGS_REG))])
+ (set (reg:CCZ FLAGS_REG) (compare:CCZ (match_dup 2) (const_int 0)))]
{
+ operands[0] = force_reg (<MODE>mode, operands[0]);
operands[2] = gen_reg_rtx (<MODE>mode);
})
I don't think we can count on a follow-up split to lower ANDN for
!TARGET_BMI case, it is also a pre-reload splitter.
Please emit ANDN only for TARGET_BMI and NOT/AND for !TARGET_BMI instead.
Uros.
> Thanks in advance,
> Roger
> --
>
