On Mon, Aug 15, 2022 at 12:12:02PM +0200, Jakub Jelinek via Gcc-patches wrote:
> Hi!
>
> The following patch implements a new builtin, __builtin_issignaling,
> which can be used to implement the ISO/IEC TS 18661-1 issignaling
> macro.
I haven't looked in detail at the patch, but from the description I think it
needs a way for machine dependent parts to optimize this for a given mode when
various switches are used.
For example on the PowerPC (and at least older AMD processors) it can often
times be expensive to move data from a floating point register to a GPR
register to do the masking operation. I implemented special purpose
recognizers a few years ago to speed up the SFmode math library to recognize
when the glibc tests were being done.
If the machine has a faster way to implement it, it should be allowed to do
this.
On some of the PowerPC's, I might want to generate code like (note, I might
have some of the tests backwards, but the idea is test if the value is a NaN,
and if it is a NaN, look at the signalling bit. Otherwise return 0:
if (__builtin_isnan (x)) {
long long mantissa = <extract mantissa>
return ~((mantissa >> 52) & 1);
} else {
return 0;
}
That way it doesn't have to do a direct move to a GPR register to do the
extraction in general.
For SFmode/DFmode, you should be able to optimize it to something like to avoid
any explicit jumps on a power10 (note, I may have some of the tests/shifts
wrong, but that is the general method you could use):
static int inline
is_signalling_nan (double value)
{
int exponent = __builtin_vec_scalar_extract_exp (value);
long long mantissa = __builtin_vec_scalar_extract_sig (value);
return (mantissa >> 52) & (exponent == 0);
}
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: meiss...@linux.ibm.com
