On 9/12/22 01:35, Richard Biener via Gcc-patches wrote:
On Sun, Sep 11, 2022 at 10:51 PM Takayuki 'January June' Suwa via
Gcc-patches <gcc-patches@gcc.gnu.org> wrote:
Hi,
Many RISC machines, as we know, have some restrictions on placing
register-width constants in the source of load-immediate machine instructions,
so the target must provide a solution for that in the machine description.
A naive way would be to solve it early, ie. to replace with read constants
pooled in memory when expanding to RTL.
Alternatively, a more fancy approach would be to forgo placement in the constant pool
until somewhere before the reload/LRA eg. the "split1" pass to give the
optimization passes that involve immediates a chance to work.
If we choose the latter, we can expect better results with RTL if-conversion,
constant folding, etc., but it often propagates constants that are too large in
size to resolve to a simple load-immediate instruction.
This is because constant propagation has no way of telling about it, so this
patch provides it.
What does prevent other passes like fwprop, CSE and PRE from doing the
same propagation? Can that be the solution for
constant propagation as well?
I would think this should be driven by costing rather than a new hook.
I'm pretty sure we already use costing to determine some of this stuff
for CSE/PRE.
jeff
