Ramana Radhakrishnan wrote: > PR51819 is a case where we were actually putting out alignment hints > for the wrong memory size. The attached patch corrects this and > another latent issue that I spotted.
Your patch did: /* Only certain alignment specifiers are supported by the hardware. */ if (memsize == 16 && (align % 32) == 0) align_bits = 256; - else if ((memsize == 8 || memsize == 16) && (align % 16) == 0) + else if (memsize == 16 && (align % 16) == 0) align_bits = 128; - else if ((align % 8) == 0) + else if (memsize >= 8 && (align % 8) == 0) align_bits = 64; else align_bits = 0; However, I'm still seeing incorrect memory hints (with an add-on patch): Error: bad alignment -- `vld1.64 {d18-d19},[r3:256]' The ISA document specifies the following supported alignment hints: 64 8-byte alignment 128 16-byte alignment, available only if <list> contains two or four registers 256 32-byte alignment, available only if <list> contains four registers Shouldn't the check be implemented along the following lines? if (memsize == 32 && (align % 32) == 0) align_bits = 256; else if ((memsize == 16 || memsize == 32) && (align % 16) == 0) align_bits = 128; else if (memsize >= 8 && (align % 8) == 0) align_bits = 64; else align_bits = 0; Bye, Ulrich -- Dr. Ulrich Weigand GNU Toolchain for Linux on System z and Cell BE ulrich.weig...@de.ibm.com