On Sun, Nov 6, 2022 at 8:56 PM Kong, Lingling via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Hi, > The patches aimed to add Intel RAO-INT. > > The information is based on newly released > Intel Architecture Instruction Set Extensions and Future Features. > > The document comes following: > https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html. > > OK for trunk? Ok. > > gcc/ChangeLog: > > * common/config/i386/cpuinfo.h (get_available_features): > Detect raoint. > * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_RAOINT_SET, > OPTION_MASK_ISA2_RAOINT_UNSET): New. > (ix86_handle_option): Handle -mraoint. > * common/config/i386/i386-cpuinfo.h (enum processor_features): > Add FEATURE_RAOINT. > * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for > raoint. > * config.gcc: Add raointintrin.h > * config/i386/cpuid.h (bit_RAOINT): New. > * config/i386/i386-builtin.def (BDESC): Add new builtins. > * config/i386/i386-c.cc (ix86_target_macros_internal): Define > __RAOINT__. > * config/i386/i386-isa.def (RAOINT): Add DEF_PTA(RAOINT). > * config/i386/i386-options.cc (ix86_valid_target_attribute_inner_p): > Add -mraoint. > * config/i386/sync.md (rao_a<raointop><mode>): New define insn. > * config/i386/i386.opt: Add option -mraoint. > * config/i386/x86gprintrin.h: Include raointintrin.h. > * doc/extend.texi: Document raoint. > * doc/invoke.texi: Document -mraoint. > * doc/sourcebuild.texi: Document target raoint. > * config/i386/raointintrin.h: New file. > > gcc/testsuite/ChangeLog: > > * g++.dg/other/i386-2.C: Add -mraoint. > * g++.dg/other/i386-3.C: Ditto. > * gcc.target/i386/funcspec-56.inc: Add new target attribute. > * gcc.target/i386/sse-12.c: Add -mraoint. > * gcc.target/i386/sse-13.c: Ditto. > * gcc.target/i386/sse-14.c: Ditto. > * gcc.target/i386/sse-22.c: Add raoint target. > * gcc.target/i386/sse-23.c: Ditto. > * lib/target-supports.exp: Add check_effective_target_raoint. > * gcc.target/i386/rao-helper.h: New test. > * gcc.target/i386/raoint-1.c: Ditto. > * gcc.target/i386/raoint-aadd-2.c: Ditto. > * gcc.target/i386/raoint-aand-2.c: Ditto. > * gcc.target/i386/raoint-aor-2.c: Ditto. > * gcc.target/i386/raoint-axor-2.c: Ditto. > * gcc.target/i386/x86gprintrin-1.c: Ditto. > * gcc.target/i386/x86gprintrin-2.c: Ditto. > * gcc.target/i386/x86gprintrin-3.c: Ditto. > * gcc.target/i386/x86gprintrin-4.c: Ditto. > * gcc.target/i386/x86gprintrin-5.c: Ditto. > --- > gcc/common/config/i386/cpuinfo.h | 2 + > gcc/common/config/i386/i386-common.cc | 15 +++ > gcc/common/config/i386/i386-cpuinfo.h | 1 + > gcc/common/config/i386/i386-isas.h | 1 + > gcc/config.gcc | 3 +- > gcc/config/i386/cpuid.h | 1 + > gcc/config/i386/i386-builtin.def | 10 ++ > gcc/config/i386/i386-c.cc | 2 + > gcc/config/i386/i386-isa.def | 1 + > gcc/config/i386/i386-options.cc | 4 +- > gcc/config/i386/i386.opt | 4 + > gcc/config/i386/raointintrin.h | 101 ++++++++++++++++++ > gcc/config/i386/sync.md | 16 +++ > gcc/config/i386/x86gprintrin.h | 2 + > gcc/doc/extend.texi | 5 + > gcc/doc/invoke.texi | 11 +- > gcc/doc/sourcebuild.texi | 3 + > gcc/testsuite/g++.dg/other/i386-2.C | 2 +- > gcc/testsuite/g++.dg/other/i386-3.C | 2 +- > gcc/testsuite/gcc.target/i386/funcspec-56.inc | 2 + > gcc/testsuite/gcc.target/i386/rao-helper.h | 79 ++++++++++++++ > gcc/testsuite/gcc.target/i386/raoint-1.c | 31 ++++++ > gcc/testsuite/gcc.target/i386/raoint-aadd-2.c | 24 +++++ > gcc/testsuite/gcc.target/i386/raoint-aand-2.c | 25 +++++ > gcc/testsuite/gcc.target/i386/raoint-aor-2.c | 25 +++++ > gcc/testsuite/gcc.target/i386/raoint-axor-2.c | 25 +++++ > gcc/testsuite/gcc.target/i386/sse-12.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-13.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-14.c | 2 +- > gcc/testsuite/gcc.target/i386/sse-22.c | 4 +- > gcc/testsuite/gcc.target/i386/sse-23.c | 2 +- > .../gcc.target/i386/x86gprintrin-1.c | 2 +- > .../gcc.target/i386/x86gprintrin-2.c | 2 +- > .../gcc.target/i386/x86gprintrin-3.c | 2 +- > .../gcc.target/i386/x86gprintrin-4.c | 4 +- > .../gcc.target/i386/x86gprintrin-5.c | 4 +- > gcc/testsuite/lib/target-supports.exp | 11 ++ > 37 files changed, 413 insertions(+), 21 deletions(-) create mode 100644 > gcc/config/i386/raointintrin.h create mode 100644 > gcc/testsuite/gcc.target/i386/rao-helper.h > create mode 100644 gcc/testsuite/gcc.target/i386/raoint-1.c > create mode 100644 gcc/testsuite/gcc.target/i386/raoint-aadd-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/raoint-aand-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/raoint-aor-2.c > create mode 100644 gcc/testsuite/gcc.target/i386/raoint-axor-2.c > > diff --git a/gcc/common/config/i386/cpuinfo.h > b/gcc/common/config/i386/cpuinfo.h > index 42c25b8a636..df3500adc83 100644 > --- a/gcc/common/config/i386/cpuinfo.h > +++ b/gcc/common/config/i386/cpuinfo.h > @@ -850,6 +850,8 @@ get_available_features (struct __processor_model > *cpu_model, > set_feature(FEATURE_CMPCCXADD); > if (edx & bit_PREFETCHI) > set_feature (FEATURE_PREFETCHI); > + if (eax & bit_RAOINT) > + set_feature (FEATURE_RAOINT); > if (avx_usable) > { > if (eax & bit_AVXVNNI) > diff --git a/gcc/common/config/i386/i386-common.cc > b/gcc/common/config/i386/i386-common.cc > index c828ae5b7d7..60a193a651c 100644 > --- a/gcc/common/config/i386/i386-common.cc > +++ b/gcc/common/config/i386/i386-common.cc > @@ -113,6 +113,7 @@ along with GCC; see the file COPYING3. If not see > #define OPTION_MASK_ISA2_CMPCCXADD_SET OPTION_MASK_ISA2_CMPCCXADD #define > OPTION_MASK_ISA2_AMX_FP16_SET OPTION_MASK_ISA2_AMX_FP16 #define > OPTION_MASK_ISA2_PREFETCHI_SET OPTION_MASK_ISA2_PREFETCHI > +#define OPTION_MASK_ISA2_RAOINT_SET OPTION_MASK_ISA2_RAOINT > > /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same > as -msse4.2. */ > @@ -289,6 +290,7 @@ along with GCC; see the file COPYING3. If not see > #define OPTION_MASK_ISA2_CMPCCXADD_UNSET OPTION_MASK_ISA2_CMPCCXADD #define > OPTION_MASK_ISA2_AMX_FP16_UNSET OPTION_MASK_ISA2_AMX_FP16 #define > OPTION_MASK_ISA2_PREFETCHI_UNSET OPTION_MASK_ISA2_PREFETCHI > +#define OPTION_MASK_ISA2_RAOINT_UNSET OPTION_MASK_ISA2_RAOINT > > /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same > as -mno-sse4.1. */ > @@ -1226,6 +1228,19 @@ ix86_handle_option (struct gcc_options *opts, > } > return true; > > + case OPT_mraoint: > + if (value) > + { > + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_RAOINT_SET; > + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_SET; > + } > + else > + { > + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_RAOINT_UNSET; > + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_RAOINT_UNSET; > + } > + return true; > + > case OPT_mfma: > if (value) > { > diff --git a/gcc/common/config/i386/i386-cpuinfo.h > b/gcc/common/config/i386/i386-cpuinfo.h > index c06f089b0c5..345fda648ff 100644 > --- a/gcc/common/config/i386/i386-cpuinfo.h > +++ b/gcc/common/config/i386/i386-cpuinfo.h > @@ -251,6 +251,7 @@ enum processor_features > FEATURE_CMPCCXADD, > FEATURE_AMX_FP16, > FEATURE_PREFETCHI, > + FEATURE_RAOINT, > CPU_FEATURE_MAX > }; > > diff --git a/gcc/common/config/i386/i386-isas.h > b/gcc/common/config/i386/i386-isas.h > index 8648ea6903c..ba2c2d94534 100644 > --- a/gcc/common/config/i386/i386-isas.h > +++ b/gcc/common/config/i386/i386-isas.h > @@ -183,4 +183,5 @@ ISA_NAMES_TABLE_START > ISA_NAMES_TABLE_ENTRY("cmpccxadd", FEATURE_CMPCCXADD, P_NONE, > "-mcmpccxadd") > ISA_NAMES_TABLE_ENTRY("amx-fp16", FEATURE_AMX_FP16, P_NONE, "-mamx-fp16") > ISA_NAMES_TABLE_ENTRY("prefetchi", FEATURE_PREFETCHI, P_NONE, > "-mprefetchi") > + ISA_NAMES_TABLE_ENTRY("raoint", FEATURE_RAOINT, P_NONE, "-mraoint") > ISA_NAMES_TABLE_END > diff --git a/gcc/config.gcc b/gcc/config.gcc index 03c1523f7af..ceaeaebf059 > 100644 > --- a/gcc/config.gcc > +++ b/gcc/config.gcc > @@ -423,7 +423,8 @@ i[34567]86-*-* | x86_64-*-*) > hresetintrin.h keylockerintrin.h avxvnniintrin.h > mwaitintrin.h avx512fp16intrin.h avx512fp16vlintrin.h > avxifmaintrin.h avxvnniint8intrin.h > avxneconvertintrin.h > - cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h" > + cmpccxaddintrin.h amxfp16intrin.h prfchiintrin.h > + raointintrin.h" > ;; > ia64-*-*) > extra_headers=ia64intrin.h > diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index > 92583261883..a33abf35cc0 100644 > --- a/gcc/config/i386/cpuid.h > +++ b/gcc/config/i386/cpuid.h > @@ -25,6 +25,7 @@ > #define _CPUID_H_INCLUDED > > /* %eax */ > +#define bit_RAOINT (1 << 3) > #define bit_AVXVNNI (1 << 4) > #define bit_AVX512BF16 (1 << 5) > #define bit_CMPCCXADD (1 << 7) > diff --git a/gcc/config/i386/i386-builtin.def > b/gcc/config/i386/i386-builtin.def > index c272c392d03..2d683514f87 100644 > --- a/gcc/config/i386/i386-builtin.def > +++ b/gcc/config/i386/i386-builtin.def > @@ -415,6 +415,16 @@ BDESC (OPTION_MASK_ISA_AVX512BW, 0, > CODE_FOR_avx512bw_truncatev32hiv32qi2_mask_s > BDESC (0, OPTION_MASK_ISA2_AVX512FP16, CODE_FOR_avx512f_loadhf_mask, > "__builtin_ia32_loadsh_mask", IX86_BUILTIN_LOADSH_MASK, UNKNOWN, (int) > V8HF_FTYPE_PCFLOAT16_V8HF_UQI) BDESC (0, OPTION_MASK_ISA2_AVX512FP16, > CODE_FOR_avx512f_storehf_mask, "__builtin_ia32_storesh_mask", > IX86_BUILTIN_STORESH_MASK, UNKNOWN, (int) VOID_FTYPE_PCFLOAT16_V8HF_UQI) > > +/* RAOINT */ > +BDESC (0, OPTION_MASK_ISA2_RAOINT, CODE_FOR_rao_aaddsi, > +"__builtin_ia32_aadd32", IX86_BUILTIN_AADD32, UNKNOWN, (int) > +VOID_FTYPE_PINT_INT) BDESC (0, OPTION_MASK_ISA2_RAOINT, > +CODE_FOR_rao_aandsi, "__builtin_ia32_aand32", IX86_BUILTIN_AAND32, > +UNKNOWN, (int) VOID_FTYPE_PINT_INT) BDESC (0, OPTION_MASK_ISA2_RAOINT, > +CODE_FOR_rao_aorsi, "__builtin_ia32_aor32", IX86_BUILTIN_AOR32, > +UNKNOWN, (int) VOID_FTYPE_PINT_INT) BDESC (0, OPTION_MASK_ISA2_RAOINT, > +CODE_FOR_rao_axorsi, "__builtin_ia32_axor32", IX86_BUILTIN_AXOR32, > +UNKNOWN, (int) VOID_FTYPE_PINT_INT) BDESC (OPTION_MASK_ISA_64BIT, > +OPTION_MASK_ISA2_RAOINT, CODE_FOR_rao_aadddi, "__builtin_ia32_aadd64", > +IX86_BUILTIN_AADD64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG) > +BDESC (OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_RAOINT, > +CODE_FOR_rao_aanddi, "__builtin_ia32_aand64", IX86_BUILTIN_AAND64, > +UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG) BDESC > +(OPTION_MASK_ISA_64BIT, OPTION_MASK_ISA2_RAOINT, CODE_FOR_rao_aordi, > +"__builtin_ia32_aor64", IX86_BUILTIN_AOR64, UNKNOWN, (int) > +VOID_FTYPE_PLONGLONG_LONGLONG) BDESC (OPTION_MASK_ISA_64BIT, > +OPTION_MASK_ISA2_RAOINT, CODE_FOR_rao_axordi, "__builtin_ia32_axor64", > +IX86_BUILTIN_AXOR64, UNKNOWN, (int) VOID_FTYPE_PLONGLONG_LONGLONG) > + > /* RDPKRU and WRPKRU. */ > BDESC (OPTION_MASK_ISA_PKU, 0, CODE_FOR_rdpkru, "__builtin_ia32_rdpkru", > IX86_BUILTIN_RDPKRU, UNKNOWN, (int) UNSIGNED_FTYPE_VOID) BDESC > (OPTION_MASK_ISA_PKU, 0, CODE_FOR_wrpkru, "__builtin_ia32_wrpkru", > IX86_BUILTIN_WRPKRU, UNKNOWN, (int) VOID_FTYPE_UNSIGNED) diff --git > a/gcc/config/i386/i386-c.cc b/gcc/config/i386/i386-c.cc index > c92796281e0..a877d24148d 100644 > --- a/gcc/config/i386/i386-c.cc > +++ b/gcc/config/i386/i386-c.cc > @@ -666,6 +666,8 @@ ix86_target_macros_internal (HOST_WIDE_INT isa_flag, > def_or_undef (parse_in, "__AMX_FP16__"); > if (isa_flag2 & OPTION_MASK_ISA2_PREFETCHI) > def_or_undef (parse_in, "__PREFETCHI__"); > + if (isa_flag2 & OPTION_MASK_ISA2_RAOINT) > + def_or_undef (parse_in, "__RAOINT__"); > if (TARGET_IAMCU) > { > def_or_undef (parse_in, "__iamcu"); diff --git > a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index > f234dcc37d7..63a2490316a 100644 > --- a/gcc/config/i386/i386-isa.def > +++ b/gcc/config/i386/i386-isa.def > @@ -115,3 +115,4 @@ DEF_PTA(AVXNECONVERT) > DEF_PTA(CMPCCXADD) > DEF_PTA(AMX_FP16) > DEF_PTA(PREFETCHI) > +DEF_PTA(RAOINT) > diff --git a/gcc/config/i386/i386-options.cc > b/gcc/config/i386/i386-options.cc index 633d5dd7eea..10c7a3bb13e 100644 > --- a/gcc/config/i386/i386-options.cc > +++ b/gcc/config/i386/i386-options.cc > @@ -235,7 +235,8 @@ static struct ix86_target_opts isa2_opts[] = > { "-mavxneconvert", OPTION_MASK_ISA2_AVXNECONVERT }, > { "-mcmpccxadd", OPTION_MASK_ISA2_CMPCCXADD }, > { "-mamx-fp16", OPTION_MASK_ISA2_AMX_FP16 }, > - { "-mprefetchi", OPTION_MASK_ISA2_PREFETCHI } > + { "-mprefetchi", OPTION_MASK_ISA2_PREFETCHI }, > + { "-mraoint", OPTION_MASK_ISA2_RAOINT } > }; > static struct ix86_target_opts isa_opts[] = { @@ -1090,6 +1091,7 @@ > ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char > *p_strings[], > IX86_ATTR_ISA ("cmpccxadd", OPT_mcmpccxadd), > IX86_ATTR_ISA ("amx-fp16", OPT_mamx_fp16), > IX86_ATTR_ISA ("prefetchi", OPT_mprefetchi), > + IX86_ATTR_ISA ("raoint", OPT_mraoint), > > /* enum options */ > IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), > diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index > 1d91103cd54..415c52e1bb4 100644 > --- a/gcc/config/i386/i386.opt > +++ b/gcc/config/i386/i386.opt > @@ -1242,3 +1242,7 @@ Support AMX-FP16 built-in functions and code generation. > mprefetchi > Target Mask(ISA2_PREFETCHI) Var(ix86_isa_flags2) Save Support PREFETCHI > built-in functions and code generation. > + > +mraoint > +Target Mask(ISA2_RAOINT) Var(ix86_isa_flags2) Save Support RAOINT > +built-in functions and code generation. > diff --git a/gcc/config/i386/raointintrin.h b/gcc/config/i386/raointintrin.h > new file mode 100644 index 00000000000..3d966573f23 > --- /dev/null > +++ b/gcc/config/i386/raointintrin.h > @@ -0,0 +1,101 @@ > +/* Copyright (C) 2019-2022 Free Software Foundation, Inc. > + > + This file is part of GCC. > + > + GCC is free software; you can redistribute it and/or modify > + it under the terms of the GNU General Public License as published by > + the Free Software Foundation; either version 3, or (at your option) > + any later version. > + > + GCC is distributed in the hope that it will be useful, > + but WITHOUT ANY WARRANTY; without even the implied warranty of > + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + GNU General Public License for more details. > + > + Under Section 7 of GPL version 3, you are granted additional > + permissions described in the GCC Runtime Library Exception, version > + 3.1, as published by the Free Software Foundation. > + > + You should have received a copy of the GNU General Public License and > + a copy of the GCC Runtime Library Exception along with this program; > + see the files COPYING3 and COPYING.RUNTIME respectively. If not, see > + <http://www.gnu.org/licenses/>. */ > + > +#ifndef _X86GPRINTRIN_H_INCLUDED > +#error "Never use <raointintrin.h> directly; include <x86gprintrin.h> > instead." > +#endif // _X86GPRINTRIN_H_INCLUDED > + > +#ifndef __RAOINTINTRIN_H_INCLUDED > +#define __RAOINTINTRIN_H_INCLUDED > + > +#ifndef __RAOINT__ > +#pragma GCC push_options > +#pragma GCC target("raoint") > +#define __DISABLE_RAOINT__ > +#endif /* __RAOINT__ */ > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_aadd_i32 (int *__A, int __B) > +{ > + __builtin_ia32_aadd32 ((int *)__A, __B); } > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_aand_i32 (int *__A, int __B) > +{ > + __builtin_ia32_aand32 ((int *)__A, __B); } > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_aor_i32 (int *__A, int __B) > +{ > + __builtin_ia32_aor32 ((int *)__A, __B); } > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_axor_i32 (int *__A, int __B) > +{ > + __builtin_ia32_axor32 ((int *)__A, __B); } > + > +#ifdef __x86_64__ > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_aadd_i64 (long long *__A, long long __B) { > + __builtin_ia32_aadd64 ((long long *)__A, __B); } > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_aand_i64 (long long *__A, long long __B) { > + __builtin_ia32_aand64 ((long long *)__A, __B); } > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_aor_i64 (long long *__A, long long __B) { > + __builtin_ia32_aor64 ((long long *)__A, __B); } > + > +extern __inline void > +__attribute__ ((__gnu_inline__, __always_inline__, __artificial__)) > +_axor_i64 (long long *__A, long long __B) { > + __builtin_ia32_axor64 ((long long *)__A, __B); } #endif /* __x86_64__ > +*/ > + > +#ifdef __DISABLE_RAOINT__ > +#undef __DISABLE_RAOINT__ > +#pragma GCC pop_options > +#endif /* __DISABLE_RAOINT__ */ > + > +#endif /* __RAOINTINTRIN_H_INCLUDED */ > + > diff --git a/gcc/config/i386/sync.md b/gcc/config/i386/sync.md index > 98a39b4e5f0..af9a1f43741 100644 > --- a/gcc/config/i386/sync.md > +++ b/gcc/config/i386/sync.md > @@ -40,6 +40,9 @@ > > ;; For CMPccXADD support > UNSPECV_CMPCCXADD > + > + ;; For RAOINT support > + UNSPECV_RAOINT > ]) > > (define_expand "sse2_lfence" > @@ -785,6 +788,19 @@ > "" > "%K3xchg{<imodesuffix>}\t{%1, %0|%0, %1}") > > +(define_code_iterator any_plus_logic [and ior xor plus]) > +(define_code_attr plus_logic [(and "and") (ior "or") (xor "xor") (plus > +"add")]) > + > +(define_insn "rao_a<plus_logic><mode>" > + [(set (match_operand:SWI48 0 "memory_operand" "+m") > + (unspec_volatile:SWI48 > + [(any_plus_logic:SWI48 (match_dup 0) > + (match_operand:SWI48 1 "register_operand" > "r")) > + (const_int 0)] ;; MEMMODEL_RELAXED > + UNSPECV_RAOINT))] > + "TARGET_RAOINT" > + "a<plus_logic>\t{%1, %0|%0, %1}") > + > (define_insn "atomic_add<mode>" > [(set (match_operand:SWI 0 "memory_operand" "+m") > (unspec_volatile:SWI > diff --git a/gcc/config/i386/x86gprintrin.h b/gcc/config/i386/x86gprintrin.h > index a84fbe9137d..a453404073b 100644 > --- a/gcc/config/i386/x86gprintrin.h > +++ b/gcc/config/i386/x86gprintrin.h > @@ -74,6 +74,8 @@ > > #include <pkuintrin.h> > > +#include <raointintrin.h> > + > #include <rdseedintrin.h> > > #include <rtmintrin.h> > diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index > 8ac9f9108bf..33a49338bd3 100644 > --- a/gcc/doc/extend.texi > +++ b/gcc/doc/extend.texi > @@ -7090,6 +7090,11 @@ Enable/disable the generation of the AMX-FP16 > instructions. > @cindex @code{target("prefetchi")} function attribute, x86 Enable/disable > the generation of the PREFETCHI instructions. > > +@item raoint > +@itemx no-raoint > +@cindex @code{target("raoint")} function attribute, x86 Enable/disable > +the generation of the RAOINT instructions. > + > @item cld > @itemx no-cld > @cindex @code{target("cld")} function attribute, x86 diff --git > a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 5e2e1031e05..4f4171e3966 > 100644 > --- a/gcc/doc/invoke.texi > +++ b/gcc/doc/invoke.texi > @@ -1438,7 +1438,7 @@ See RS/6000 and PowerPC Options. > -mrdseed -msgx -mavx512vp2intersect -mserialize -mtsxldtrk@gol -mamx-tile > -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni@gol > -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 > @gol --mprefetchi @gol > +-mprefetchi -mraoint @gol > -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops > @gol -minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol > -mkl -mwidekl @gol @@ -32999,6 +32999,9 @@ preferred alignment to > @option{-mpreferred-stack-boundary=2}. > @need 200 > @itemx -mprefetchi > @opindex mprefetchi > +@need 200 > +@itemx -mraoint > +@opindex mraoint > These switches enable the use of instructions in the MMX, SSE, SSE2, SSE3, > SSSE3, SSE4, SSE4A, SSE4.1, SSE4.2, AVX, AVX2, AVX512F, AVX512PF, AVX512ER, > AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, @@ > -33009,9 +33012,9 @@ XSAVEOPT, XSAVEC, XSAVES, RTM, HLE, TBM, MWAITX, CLZERO, > PKU, AVX512VBMI2, GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, > MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, > AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, > WIDEKL, AVXVNNI, AVX512FP16, -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, > AMX-FP16, PREFETCHI or CLDEMOTE -extended instruction sets. Each has a > corresponding @option{-mno-} option to -disable use of these instructions. > +AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, > +RAOINT or CLDEMOTE extended instruction sets. Each has a corresponding > +@option{-mno-} option to disable use of these instructions. > > These extensions are also available as built-in functions: see > @ref{x86 Built-in Functions}, for details of the functions enabled and diff > --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index > 58adb6516ed..fae43c98712 100644 > --- a/gcc/doc/sourcebuild.texi > +++ b/gcc/doc/sourcebuild.texi > @@ -2538,6 +2538,9 @@ The x86-64 target linker supports PIE with copy reloc. > @item prefetchi > Target supports the execution of @code{prefetchi} instructions. > > +@item raoint > +Target supports the execution of @code{raoint} instructions. > + > @item rdrand > Target supports x86 @code{rdrand} instruction. > > diff --git a/gcc/testsuite/g++.dg/other/i386-2.C > b/gcc/testsuite/g++.dg/other/i386-2.C > index ec3b1864ec0..fc910cec78a 100644 > --- a/gcc/testsuite/g++.dg/other/i386-2.C > +++ b/gcc/testsuite/g++.dg/other/i386-2.C > @@ -1,5 +1,5 @@ > /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ > -/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx -mavx2 > -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm -mlwp > -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr > -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 > -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma > -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq > -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig > -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk > -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 > -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi" } > */ > +/* { dg-options "-O -pedantic-errors -march=k8 -msse4a -m3dnow -mavx > +-mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 > +-mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw > +-madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf > +-msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq > +-mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi -mavx512vbmi2 > +-mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb -mmwaitx > +-mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd > +-mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk > +-mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 > +-mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 > +-mprefetchi -mraoint" } */ > > /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, > xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff > --git a/gcc/testsuite/g++.dg/other/i386-3.C > b/gcc/testsuite/g++.dg/other/i386-3.C > index 542275ca057..64741b11685 100644 > --- a/gcc/testsuite/g++.dg/other/i386-3.C > +++ b/gcc/testsuite/g++.dg/other/i386-3.C > @@ -1,5 +1,5 @@ > /* { dg-do compile { target i?86-*-* x86_64-*-* } } */ > -/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow -mavx > -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 -mtbm > -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx -mfxsr > -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha -mprefetchwt1 > -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma > -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq > -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig > -mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize -mtsxldtrk > -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni -mavx512fp16 > -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi" } > */ > +/* { dg-options "-O -fkeep-inline-functions -march=k8 -msse4a -m3dnow > +-mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi > +-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed > +-mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd > +-mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt > +-mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi > +-mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb > +-mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig > +-mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize > +-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni > +-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd > +-mamx-fp16 -mprefetchi -mraoint" } */ > > /* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h, fma4intrin.h, > xopintrin.h, abmintrin.h, bmiintrin.h, tbmintrin.h, lwpintrin.h, diff > --git a/gcc/testsuite/gcc.target/i386/funcspec-56.inc > b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > index 1dca8b060d3..7eb18c6952d 100644 > --- a/gcc/testsuite/gcc.target/i386/funcspec-56.inc > +++ b/gcc/testsuite/gcc.target/i386/funcspec-56.inc > @@ -86,6 +86,7 @@ extern void test_avxneconvert (void) > __attribute__((__target__("avxneconvert")) > extern void test_cmpccxadd (void) > __attribute__((__target__("cmpccxadd"))); > extern void test_amx_fp16 (void) > __attribute__((__target__("amx-fp16"))); > extern void test_prefetchi (void) > __attribute__((__target__("prefetchi"))); > +extern void test_raoint (void) > __attribute__((__target__("raoint"))); > > extern void test_no_sgx (void) > __attribute__((__target__("no-sgx"))); > extern void test_no_avx5124fmaps(void) > __attribute__((__target__("no-avx5124fmaps"))); > @@ -173,6 +174,7 @@ extern void test_no_avxneconvert (void) > __attribute__((__target__("no-avxneconv > extern void test_no_cmpccxadd (void) > __attribute__((__target__("no-cmpccxadd"))); > extern void test_no_amx_fp16 (void) > __attribute__((__target__("no-amx-fp16"))); > extern void test_no_prefetchi (void) > __attribute__((__target__("no-prefetchi"))); > +extern void test_no_raoint (void) > __attribute__((__target__("no-raoint"))); > > extern void test_arch_nocona (void) > __attribute__((__target__("arch=nocona"))); > extern void test_arch_core2 (void) > __attribute__((__target__("arch=core2"))); > diff --git a/gcc/testsuite/gcc.target/i386/rao-helper.h > b/gcc/testsuite/gcc.target/i386/rao-helper.h > new file mode 100644 > index 00000000000..df385516f48 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/rao-helper.h > @@ -0,0 +1,79 @@ > +#include <immintrin.h> > +#include <stdint.h> > +#include <pthread.h> > +#include <string.h> > +#ifdef DEBUG > +#include <stdio.h> > +#endif > +#include "cpuid.h" > + > +typedef struct { > + uint32_t id; /* filled in by launch_threads. */ } state_t; > + > +static pthread_t* threads = 0; > +static state_t* thread_state = 0; > +static const unsigned int num_threads = 4; > + > +static void* threads_worker (state_t *tstate); > + > +void launch_threads (uint32_t nthreads, > + void* (*worker)(state_t*), > + state_t* tstate_proto) { > + int i; > + thread_state = malloc (sizeof (state_t) *nthreads); > + threads = malloc (sizeof (pthread_t) *nthreads); > + memset (threads, 0, sizeof (pthread_t) *nthreads); > + for(i = 0; i < nthreads; i++) > + { > + memcpy (thread_state + i, tstate_proto, sizeof (state_t)); > + thread_state[i].id = i; > + pthread_create (threads+i, NULL, > + (void* (*)(void*))worker, > + (void*) (thread_state+i)); > + } > +} > + > +void wait() > +{ > + int i; > + for(i = 0; i < num_threads; i++) > + pthread_join (threads[i], 0); > + free (threads); > + threads = 0; > + free (thread_state); > + thread_state = 0; > +} > + > +#ifndef DO_TEST > +#define DO_TEST do_test > +static void rao_test (void); > +__attribute__ ((noinline)) > +static void > +do_test (void) > +{ > + state_t tstate_proto; > + launch_threads(num_threads, threads_worker, &tstate_proto); > + wait(); > + rao_test (); > +} > +#endif > + > +int > +main() > +{ > + if (__builtin_cpu_supports ("raoint")) > + { > + DO_TEST (); > +#ifdef DEBUG > + printf ("PASSED\n"); > +#endif > + } > +#ifdef DEBUG > + else > + printf ("SKIPPED\n"); > +#endif > + > + return 0; > +} > diff --git a/gcc/testsuite/gcc.target/i386/raoint-1.c > b/gcc/testsuite/gcc.target/i386/raoint-1.c > new file mode 100644 > index 00000000000..d4f880ee304 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-1.c > @@ -0,0 +1,31 @@ > +/* { dg-do compile } */ > +/* { dg-options "-mraoint -O2" } */ > +/* { dg-final { scan-assembler-times "aadd" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aand" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aor" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "axor" 2 { target {! ia32 } } } } > +*/ > +/* { dg-final { scan-assembler-times "aadd" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "aand" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "aor" 1 { target ia32 } } } */ > +/* { dg-final { scan-assembler-times "axor" 1 { target ia32 } } } */ > +#include <immintrin.h> > + > +volatile int x; > +volatile long long y; > +int *a; > +long long *b; > + > +void extern > +rao_int_test (void) > +{ > + _aadd_i32 (a, x); > + _aand_i32 (a, x); > + _aor_i32 (a, x); > + _axor_i32 (a, x); > +#ifdef __x86_64__ > + _aadd_i64 (b, y); > + _aand_i64 (b, y); > + _aor_i64 (b, y); > + _axor_i64 (b, y); > +#endif > +} > diff --git a/gcc/testsuite/gcc.target/i386/raoint-aadd-2.c > b/gcc/testsuite/gcc.target/i386/raoint-aadd-2.c > new file mode 100644 > index 00000000000..8ae9bc25b17 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-aadd-2.c > @@ -0,0 +1,24 @@ > +/* { dg-do run { target { *-*-linux* && { ! ia32 } } } }*/ > +/* { dg-require-effective-target raoint }*/ > +/* { dg-options "-pthread -O2 -mraoint" }*/ #include "rao-helper.h" > + > +const unsigned int inc_val = 3; > +const unsigned int num_iters= 1000000; > +static long long shared_val = 0; > + > +static > +void* threads_worker (state_t *tstate) > +{ > + int i; > + for (i = 0; i < num_iters; i++) > + _aadd_i64 (&shared_val, inc_val); > + return 0; > +} > + > +static void > +rao_test (void) > +{ > + if (shared_val != num_iters * num_threads * inc_val) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/raoint-aand-2.c > b/gcc/testsuite/gcc.target/i386/raoint-aand-2.c > new file mode 100644 > index 00000000000..40bc1d71621 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-aand-2.c > @@ -0,0 +1,25 @@ > +/* { dg-do run { target { *-*-linux* && { ! ia32 } } } }*/ > +/* { dg-require-effective-target raoint }*/ > +/* { dg-options "-pthread -O2 -mraoint" }*/ #include "rao-helper.h" > + > +const unsigned int num_iters= 1000000; > +unsigned int thread_val[4] = { 0xffffff5a, 0xffff96ff, 0xff73ffff, > +0xceffffff }; static long long shared_val = 0xffffffff; unsigned int > +expected_val = 0xce73965a; > + > +static void* > +threads_worker (state_t *tstate) > +{ > + int i; > + unsigned int val = thread_val[tstate->id]; > + for (i = 0; i < num_iters; i++) > + _aand_i64 (&shared_val, val); > +} > + > +static void > +rao_test(void) > +{ > + if (shared_val != expected_val) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/raoint-aor-2.c > b/gcc/testsuite/gcc.target/i386/raoint-aor-2.c > new file mode 100644 > index 00000000000..ec7f7cc1689 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-aor-2.c > @@ -0,0 +1,25 @@ > +/* { dg-do run { target { *-*-linux* && { ! ia32 } } } }*/ > +/* { dg-require-effective-target raoint }*/ > +/* { dg-options "-pthread -O2 -mraoint" }*/ #include "rao-helper.h" > + > +const unsigned int num_iters= 1000000; > +unsigned int thread_val[4] = { 0x5a, 0x9600, 0x730000, 0xce000000 }; > +static long long shared_val = 0; unsigned int expected_val = > +0xce73965a; > + > +static void* > +threads_worker (state_t *tstate) > +{ > + int i; > + unsigned int val = thread_val[tstate->id]; > + for (i = 0; i < num_iters; i++) > + _aor_i64 (&shared_val, val); > +} > + > +static void > +rao_test (void) > +{ > + if (shared_val != expected_val) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/raoint-axor-2.c > b/gcc/testsuite/gcc.target/i386/raoint-axor-2.c > new file mode 100644 > index 00000000000..a875592a486 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/raoint-axor-2.c > @@ -0,0 +1,25 @@ > +/* { dg-do run { target { *-*-linux* && { ! ia32 } } } }*/ > +/* { dg-require-effective-target raoint }*/ > +/* { dg-options "-pthread -O2 -mraoint" }*/ #include "rao-helper.h" > + > +const unsigned int num_iters= 1000001; > +unsigned int thread_val[4] = { 0x5a, 0x9600, 0x730000, 0xce000000 }; > +static long long shared_val = 0; unsigned int expected_val = > +0xce73965a; > + > +static void* > +threads_worker (state_t *tstate) > +{ > + int i; > + unsigned int val = thread_val[tstate->id]; > + for (i = 0; i < num_iters; i++) > + _axor_i64 (&shared_val, val); > +} > + > +static void > +rao_test (void) > +{ > + if (shared_val != expected_val) > + abort (); > +} > diff --git a/gcc/testsuite/gcc.target/i386/sse-12.c > b/gcc/testsuite/gcc.target/i386/sse-12.c > index 8c556f3fcc5..c5b2a18945c 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-12.c > +++ b/gcc/testsuite/gcc.target/i386/sse-12.c > @@ -3,7 +3,7 @@ > popcntintrin.h gfniintrin.h and mm_malloc.h are usable > with -O -std=c89 -pedantic-errors. */ > /* { dg-do compile } */ > -/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow > -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi -mbmi2 > -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw -madx > -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha > -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512bw -mavx512dq -mavx512vl > -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw > -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni > -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd > -mavx512vp2intersect -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 > -mkl -mwidekl -mavxvnni -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 > -mprefetchi" } */ > +/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -msse4a -m3dnow > +-mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi > +-mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed > +-mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd > +-mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves -mclflushopt > +-mavx512bw -mavx512dq -mavx512vl -mavx512vbmi -mavx512vbmi2 > +-mavx512ifma -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb > +-mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mavx512bitalg -mpconfig > +-mwbnoinvd -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize > +-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni > +-mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 -mprefetchi -mraoint" > +} */ > > #include <x86intrin.h> > > diff --git a/gcc/testsuite/gcc.target/i386/sse-13.c > b/gcc/testsuite/gcc.target/i386/sse-13.c > index ee5ba5ae4d5..858d5744b76 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-13.c > +++ b/gcc/testsuite/gcc.target/i386/sse-13.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -msse4a > -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi > -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw > -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha > -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512vl -mavx512dq -mavx512bw > -mavx512vbmi -mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw > -mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku -msgx > -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 -menqcmd > -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl > -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd > -mamx-fp16 -mprefetchi" } */ > +/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 > +-msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm > +-mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm > +-mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er > +-mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves > +-mclflushopt -mavx512vl -mavx512dq -mavx512bw -mavx512vbmi > +-mavx512vbmi2 -mavx512ifma -mavx5124fmaps -mavx5124vnniw > +-mavx512vpopcntdq -mavx512vp2intersect -mclwb -mmwaitx -mclzero -mpku > +-msgx -mrdpid -mgfni -mavx512bitalg -mpconfig -mwbnoinvd -mavx512bf16 > +-menqcmd -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl > +-mwidekl -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert > +-mcmpccxadd -mamx-fp16 -mprefetchi -mraoint" } */ > /* { dg-add-options bind_pic_locally } */ > > #include <mm_malloc.h> > diff --git a/gcc/testsuite/gcc.target/i386/sse-14.c > b/gcc/testsuite/gcc.target/i386/sse-14.c > index 4f3bd70d03e..18d97fea2e9 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-14.c > +++ b/gcc/testsuite/gcc.target/i386/sse-14.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -msse4a > -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm -mlzcnt -mbmi > -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm -mrdseed -mprfchw > -madx -mfxsr -mxsaveopt -mavx512f -mavx512er -mavx512cd -mavx512pf -msha > -mprefetchwt1 -mxsavec -mxsaves -mclflushopt -mavx512dq -mavx512bw -mavx512vl > -mavx512ifma -mavx512vbmi -mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw > -mavx512vpopcntdq -mclwb -mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni > -mpconfig -mwbnoinvd -mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect > -mserialize -mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl > -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 > -mprefetchi" } */ > +/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 > +-msse4a -m3dnow -mavx -mavx2 -mfma4 -mxop -maes -mpclmul -mpopcnt -mabm > +-mlzcnt -mbmi -mbmi2 -mtbm -mlwp -mfsgsbase -mrdrnd -mf16c -mfma -mrtm > +-mrdseed -mprfchw -madx -mfxsr -mxsaveopt -mavx512f -mavx512er > +-mavx512cd -mavx512pf -msha -mprefetchwt1 -mxsavec -mxsaves > +-mclflushopt -mavx512dq -mavx512bw -mavx512vl -mavx512ifma -mavx512vbmi > +-mavx512vbmi2 -mavx5124fmaps -mavx5124vnniw -mavx512vpopcntdq -mclwb > +-mmwaitx -mclzero -mpku -msgx -mrdpid -mgfni -mpconfig -mwbnoinvd > +-mavx512vl -mavx512bf16 -menqcmd -mavx512vp2intersect -mserialize > +-mtsxldtrk -mamx-tile -mamx-int8 -mamx-bf16 -mkl -mwidekl -mavxvnni > +-mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mamx-fp16 > +-mprefetchi -mraoint" } */ > /* { dg-add-options bind_pic_locally } */ > > #include <mm_malloc.h> > diff --git a/gcc/testsuite/gcc.target/i386/sse-22.c > b/gcc/testsuite/gcc.target/i386/sse-22.c > index 8bd046b19c2..0d9965e284e 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-22.c > +++ b/gcc/testsuite/gcc.target/i386/sse-22.c > @@ -103,7 +103,7 @@ > > > #ifndef DIFFERENT_PRAGMAS > -#pragma GCC target > ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,avx512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,prefetchi") > +#pragma GCC target > +("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tb > +m,lwp,fsgsbase,rdrnd,f16c,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,a > +vx512er,avx512cd,avx512pf,sha,prefetchwt1,avx512vl,avx512bw,avx512dq,av > +x512vbmi,avx512vbmi2,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcnt > +dq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,a > +mx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnnii > +nt8,avxneconvert,amx-fp16,prefetchi,raoint") > #endif > > /* Following intrinsics require immediate arguments. They @@ -220,7 +220,7 > @@ test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1) > > /* immintrin.h (AVX/AVX2/RDRND/FSGSBASE/F16C/RTM/AVX512F/SHA) */ #ifdef > DIFFERENT_PRAGMAS -#pragma GCC target > ("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,sha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,prefetchi") > +#pragma GCC target > +("avx,avx2,rdrnd,fsgsbase,f16c,rtm,avx512f,avx512er,avx512cd,avx512pf,s > +ha,avx512vl,avx512bw,avx512dq,avx512ifma,avx512vbmi,avx512vbmi2,avx5124 > +fmaps,avx5124vnniw,avx512vpopcntdq,gfni,avx512bitalg,avx512bf16,avx512v > +p2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avx > +vnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,amx-fp16,prefetchi,rao > +int") > #endif > #include <immintrin.h> > test_1 (_cvtss_sh, unsigned short, float, 1) diff --git > a/gcc/testsuite/gcc.target/i386/sse-23.c > b/gcc/testsuite/gcc.target/i386/sse-23.c > index 16ac9c9b7a4..c9bfd75aa92 100644 > --- a/gcc/testsuite/gcc.target/i386/sse-23.c > +++ b/gcc/testsuite/gcc.target/i386/sse-23.c > @@ -847,6 +847,6 @@ > #define __builtin_ia32_cmpccxadd(A, B, C, D) __builtin_ia32_cmpccxadd(A, B, > C, 1) #define __builtin_ia32_cmpccxadd64(A, B, C, D) > __builtin_ia32_cmpccxadd64(A, B, C, 1) > > -#pragma GCC target > ("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tbm,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx512f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt,avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vnniw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,vpclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2intersect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,avx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi") > +#pragma GCC target > +("sse4a,3dnow,avx,avx2,fma4,xop,aes,pclmul,popcnt,abm,lzcnt,bmi,bmi2,tb > +m,lwp,fsgsbase,rdrnd,f16c,fma,rtm,rdseed,prfchw,adx,fxsr,xsaveopt,avx51 > +2f,avx512er,avx512cd,avx512pf,sha,prefetchwt1,xsavec,xsaves,clflushopt, > +avx512bw,avx512dq,avx512vl,avx512vbmi,avx512ifma,avx5124fmaps,avx5124vn > +niw,avx512vpopcntdq,clwb,mwaitx,clzero,pku,sgx,rdpid,gfni,avx512vbmi2,v > +pclmulqdq,avx512bitalg,pconfig,wbnoinvd,avx512bf16,enqcmd,avx512vp2inte > +rsect,serialize,tsxldtrk,amx-tile,amx-int8,amx-bf16,kl,widekl,avxvnni,a > +vx512fp16,avxifma,avxvnniint8,avxneconvert,cmpccxadd,amx-fp16,prefetchi > +,raoint") > > #include <x86intrin.h> > diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c > b/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c > index 76de89d0cb7..6325ff9f5ba 100644 > --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c > +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-1.c > @@ -1,6 +1,6 @@ > /* Test that <x86gprintrin.h> is usable with -O -std=c89 -pedantic-errors. > */ > /* { dg-do compile } */ > -/* { dg-options "-O -std=c89 -pedantic-errors -march=x86-64 -madx -mbmi > -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase -mfxsr > -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt -mpku -mptwrite > -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk > -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt -mxsaves -mno-sse -mno-mmx" > } */ > +/* { dg-options "-O -std=c89 -pedantic-errors -march=x86-64 -madx -mbmi > +-mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd -mfsgsbase > +-mfxsr -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig -mpopcnt > +-mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx > +-mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec > +-mxsaveopt -mxsaves -mraoint -mno-sse -mno-mmx" } */ > /* { dg-additional-options "-mcmpccxadd -muintr" { target { ! ia32 } } } */ > > #include <x86gprintrin.h> > diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c > b/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c > index aefad77f864..9c9e87c42c7 100644 > --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c > +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-2.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O2 -Werror-implicit-function-declaration -march=x86-64 > -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd > -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig > -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx > -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt > -mxsaves -mno-sse -mno-mmx" } */ > +/* { dg-options "-O2 -Werror-implicit-function-declaration > +-march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb > +-mclzero -menqcmd -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri > +-mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed > +-mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd > +-mxsave -mxsavec -mxsaveopt -mxsaves -mraoint -mno-sse -mno-mmx" } */ > /* { dg-add-options bind_pic_locally } */ > /* { dg-additional-options "-mcmpccxadd -muintr" { target { ! ia32 } } } */ > > diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c > b/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c > index 261c9180aa0..3a3c344a78a 100644 > --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c > +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-3.c > @@ -1,5 +1,5 @@ > /* { dg-do compile } */ > -/* { dg-options "-O0 -Werror-implicit-function-declaration -march=x86-64 > -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb -mclzero -menqcmd > -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri -mmwaitx -mpconfig > -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed -mrtm -mserialize -msgx > -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd -mxsave -mxsavec -mxsaveopt > -mxsaves -mno-sse -mno-mmx" } */ > +/* { dg-options "-O0 -Werror-implicit-function-declaration > +-march=x86-64 -madx -mbmi -mbmi2 -mcldemote -mclflushopt -mclwb > +-mclzero -menqcmd -mfsgsbase -mfxsr -mhreset -mlzcnt -mlwp -mmovdiri > +-mmwaitx -mpconfig -mpopcnt -mpku -mptwrite -mrdpid -mrdrnd -mrdseed > +-mrtm -mserialize -msgx -mshstk -mtbm -mtsxldtrk -mwaitpkg -mwbnoinvd > +-mxsave -mxsavec -mxsaveopt -mxsaves -mraoint -mno-sse -mno-mmx" } */ > /* { dg-add-options bind_pic_locally } */ > /* { dg-additional-options "-mcmpccxadd -muintr" { target { ! ia32 } } } */ > > diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c > b/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c > index 7f76b870934..b1bbda31237 100644 > --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c > +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-4.c > @@ -15,9 +15,9 @@ > > #ifndef DIFFERENT_PRAGMAS > #ifdef __x86_64__ > -#pragma GCC target > ("adx,bmi,bmi2,cmpccxadd,fsgsbase,fxsr,hreset,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,uintr,xsaveopt") > +#pragma GCC target > +("adx,bmi,bmi2,cmpccxadd,fsgsbase,fxsr,hreset,lwp,lzcnt,popcnt,raoint,r > +drnd,rdseed,tbm,rtm,serialize,tsxldtrk,uintr,xsaveopt") > #else > -#pragma GCC target > ("adx,bmi,bmi2,fsgsbase,fxsr,hreset,lwp,lzcnt,popcnt,rdrnd,rdseed,tbm,rtm,serialize,tsxldtrk,xsaveopt") > +#pragma GCC target > +("adx,bmi,bmi2,fsgsbase,fxsr,hreset,lwp,lzcnt,popcnt,raoint,rdrnd,rdsee > +d,tbm,rtm,serialize,tsxldtrk,xsaveopt") > #endif > #endif > > diff --git a/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c > b/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c > index 54d826c4f46..e3ad67d1e77 100644 > --- a/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c > +++ b/gcc/testsuite/gcc.target/i386/x86gprintrin-5.c > @@ -32,9 +32,9 @@ > #define __builtin_ia32_cmpccxadd64(A, B, C, D) __builtin_ia32_cmpccxadd64(A, > B, C, 1) > > #ifdef __x86_64__ > -#pragma GCC target > ("adx,bmi,bmi2,clflushopt,clwb,clzero,cmpccxadd,enqcmd,fsgsbase,fxsr,hreset,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,uintr,xsavec,xsaveopt,xsaves,wbnoinvd") > +#pragma GCC target > +("adx,bmi,bmi2,clflushopt,clwb,clzero,cmpccxadd,enqcmd,fsgsbase,fxsr,hr > +eset,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,raoint,rdpid,rdrnd,rdseed,tbm, > +rtm,serialize,sgx,tsxldtrk,uintr,xsavec,xsaveopt,xsaves,wbnoinvd") > #else > -#pragma GCC target > ("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,hreset,lwp,lzcnt,mwaitx,pconfig,pku,popcnt,rdpid,rdrnd,rdseed,tbm,rtm,serialize,sgx,tsxldtrk,xsavec,xsaveopt,xsaves,wbnoinvd") > +#pragma GCC target > +("adx,bmi,bmi2,clflushopt,clwb,clzero,enqcmd,fsgsbase,fxsr,hreset,lwp,l > +zcnt,mwaitx,pconfig,pku,popcnt,raoint,rdpid,rdrnd,rdseed,tbm,rtm,serial > +ize,sgx,tsxldtrk,xsavec,xsaveopt,xsaves,wbnoinvd") > #endif > > #include <x86gprintrin.h> > diff --git a/gcc/testsuite/lib/target-supports.exp > b/gcc/testsuite/lib/target-supports.exp > index 30e192f4d46..c7f583d6d14 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -9571,6 +9571,17 @@ proc check_effective_target_cmpccxadd { } { > } "-mcmpccxadd" ] > } > > +# Return 1 if raoint instructions can be compiled. > +proc check_effective_target_raoint { } { > + return [check_no_compiler_messages raoint object { > + void > + _aadd_si32 (int *__A, int __B) > + { > + return __builtin_ia32_aadd32((int *)__A, __B); > + } > + } "-mraoint" ] > +} > + > # Return 1 if sse instructions can be compiled. > proc check_effective_target_sse { } { > return [check_no_compiler_messages sse object { > -- > 2.27.0 >
-- BR, Hongtao
