This patch enables generating load and store vector pair instructions when
doing certain memory copy operations when -mcpu=future is used. In doing tests
on power10, it was determined that using these instructions were problematical
in a few cases, so we disabled generating them by default. This patch
re-enabled generating these instructions if -mcpu=future is used.
The patches have been tested on the following platforms. I added the patches
for PR target/107299 that I submitted on November 2nd before doing the builds so
that GCC would build on systems using IEEE 128-bit long double.
* https://gcc.gnu.org/pipermail/gcc-patches/2022-November/604834.html
There were no regressions with doing bootstrap builds and running the regression
tests:
1) Power10 LE using --with-cpu=power10 --with-long-double-format=ieee;
2) Power10 LE using --with-cpu=power10 --with-long-double-format=ibm;
3) Power9 LE using --with-cpu=power9 --with-long-double-format=ibm; and
4) Power8 BE using --with-cpu=power8 (both 32-bit & 64-bit tested).
Can I check this patch into the GCC 13 master branch?
2022-11-09 Michael Meissner <[email protected]>
gcc/
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add
-mblock-ops-vector-pair.
(POWERPC_MASKS): Likewise.
---
gcc/config/rs6000/rs6000-cpus.def | 2 ++
1 file changed, 2 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 5eac7d97e65..e8df7927055 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -89,6 +89,7 @@
/* Flags for a potential future processor that may or may not be delivered. */
#define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_FUTURE)
/* Flags that need to be turned off if -mno-power9-vector. */
@@ -126,6 +127,7 @@
/* Mask of all options to set the default isa flags based on -mcpu=<xxx>. */
#define POWERPC_MASKS (OPTION_MASK_ALTIVEC \
+ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \
| OPTION_MASK_CMPB \
| OPTION_MASK_CRYPTO \
| OPTION_MASK_DFP \
--
2.38.1
--
Michael Meissner, IBM
PO Box 98, Ayer, Massachusetts, USA, 01432
email: [email protected]
