Hi, The patch enables have_cbrnachcc4 which is a flag in ifcvt.cc to indicate if branch by CC bits is invalid or not. As rs6000 already has "*cbranch" insn which does branching according to CC bits, the flag should be enabled and relevant branches can be optimized out. The test case illustrates the optimization.
"*cbranch" is an anonymous insn which can't be generated directly. So changing "const_int 0" to the third operand predicated by "zero_constant" won't cause ICEs as orginal patterns still can be matched. Bootstrapped and tested on powerpc64-linux BE and LE with no regressions. Is this okay for trunk? Any recommendations? Thanks a lot. ChangeLog 2022-11-16 Haochen Gui <guih...@linux.ibm.com> gcc/ * config/rs6000/rs6000.md (*cbranch): Rename to... (cbranchcc4): ...this, and set const_int 0 to the third operand. gcc/testsuite/ * gcc.target/powerpc/cbranchcc4.c: New. patch.diff diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e9e5cd1e54d..ee171f21f6a 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -13067,11 +13067,11 @@ (define_insn_and_split "*<code><mode>_cc" ;; Conditional branches. ;; These either are a single bc insn, or a bc around a b. -(define_insn "*cbranch" +(define_insn "cbranchcc4" [(set (pc) (if_then_else (match_operator 1 "branch_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") - (const_int 0)]) + (match_operand 3 "zero_constant")]) (label_ref (match_operand 0)) (pc)))] "" diff --git a/gcc/testsuite/gcc.target/powerpc/cbranchcc4.c b/gcc/testsuite/gcc.target/powerpc/cbranchcc4.c new file mode 100644 index 00000000000..1751d274bbf --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/cbranchcc4.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -fdump-rtl-ce1" } */ +/* { dg-final {scan-rtl-dump "noce_try_store_flag_constants" "ce1" } } */ + +int test (unsigned int a, unsigned int b) +{ + return (a < b ? 0 : (a > b ? 2 : 1)); +}