Jakub Jelinek <ja...@redhat.com> writes:
> On Thu, Jan 12, 2023 at 04:50:07PM +0000, Richard Sandiford wrote:
>> I'm jumping in here without fully understanding the context, so maybe this
>> is exactly your point, but: the SIMD/FP DWARF registers are supposed to be
>> size 8 regardless of which features are enabled. That's already only half
>> of the hardware register size for base Armv8-A, since Advanced SIMD registers
>> are 16 bytes in size.
>>
>> So yeah, if we're using the hardware register size then something is wrong.
>
> I'm talking about what the following compiles to
> static unsigned char dwarf_reg_size_table[__LIBGCC_DWARF_FRAME_REGISTERS__+1];
>
> void
> foo (void)
> {
> __builtin_init_dwarf_reg_size_table (dwarf_reg_size_table);
> }
> (and therefore what libgcc/unwind-dw2.c (init_dwarf_reg_size_table) as well)
> with -O2 -fbuilding-libgcc -march=armv8-a vs. -O2 -fbuilding-libgcc
> -march=armv8-a+sve
> The former is setting I think [0..31, 46, 48..63, 72..79, 96]=8, [64..71,
> 80..95]=0
> (and leaving others untouched, which keeps them 0).
> While the latter is setting [0..31, 46, 72..79, 96]=8, [64..71, 80..95]=0
> and [48..63]=cntd
Ah, interesting. So the SIMD/FP registers are OK, but the predicate
registers are causing a problem.
I think we should set the predicates to size 0 too, like we do for
call-clobbered FP registers. Predicate registers should never need
to be represented in CFI.
Thanks,
Richard
