> -----Original Message-----
> From: Andre Vieira (lists) <[email protected]>
> Sent: Wednesday, January 25, 2023 5:41 PM
> To: [email protected]
> Cc: Kyrylo Tkachov <[email protected]>; Richard Earnshaw
> <[email protected]>
> Subject: Re: [PATCH 3/3] arm: Fix MVE predicates synthesis [PR 108443]
>
> Looks like the first patch was missing a change I had made to prevent
> mve_bool_vec_to_const ICEing if called with a non-vector immediate. Now
> included.
>
> On 24/01/2023 13:56, Andre Vieira (lists) via Gcc-patches wrote:
> > Hi,
> >
> > This patch fixes the way we synthesize MVE predicate immediates and
> > fixes some other inconsistencies around predicates. For instance this
> > patch fixes the modes used in the vctp intrinsics, to couple them with
> > predicate modes with the appropriate lane numbers. For this V2QI is
> > added to represent a predicate created by vctp64q. The reason we use
> > V2QI and not for instance a V2BI with 8-bit boolean modes is because we
> > are trying to avoid having two 'INT' modes of the same size. We make
> > sure we use the V2QI mode instead of HI for any instruction working on
> > two lanes of 64-bits consuming a predicate.
> >
> > Bootstrapped on aarch64-none-linux-gnu and regression tested on
> > arm-none-eabi and armeb-none-eabi for armv8.1-m.main+mve.fp.
> >
> > OK for trunk?
> >
> > gcc/ChangeLog:
> >
> > PR target/108443
> > * config/arm/arm.h (VALID_MVE_PRED_MODE): Add V2QI.
> > * config/arm/arm.cc (thumb2_legitimate_address_p): Use HImode for
> > addressing MVE predicate modes.
> > (mve_bool_vec_to_const): Change to represent correct MVE predicate
> > format.
> > (arm_hard_regno_mode_ok): Use VALID_MVE_PRED_MODE instead of
> > checking modes.
> > (arm_vector_mode_supported_p): Likewise.
> > (arm_mode_to_pred_mode): Add V2QI.
> > * config/arm/arm-builtins.cc (UNOP_PRED_UNONE_QUALIFIERS): New
> > qualifier.
> > (UNOP_PRED_PRED_QUALIFIERS): New qualifier
> > (BINOP_PRED_UNONE_PRED_QUALIFIERS): New qualifier.
> > (v2qi_UP): New macro.
> > (v4bi_UP): New macro.
> > (v8bi_UP): New macro.
> > (v16bi_UP): New macro.
> > (arm_expand_builtin_args): Make it able to expand the new predicate
> > modes.
> > * config/arm/arm-modes.def (V2QI): New mode.
> > * config/arm/arm-simd-builtin-types.def (Pred1x16_t, Pred2x8_t
> > Pred4x4_t): Remove unused predicate builtin types.
> > * config/arm/arm_mve.h (__arm_vctp16q, __arm_vctp32q,
> __arm_vctp64q,
> > __arm_vctp8q, __arm_vpnot, __arm_vctp8q_m, __arm_vctp64q_m,
> > __arm_vctp32q_m, __arm_vctp16q_m): Use predicate modes.
> > * config/arm/arm_mve_builtins.def (vctp16q, vctp32q, vctp64q, vctp8q,
> > vpnot, vctp8q_m, vctp16q_m, vctp32q_m, vctp64q_m): Likewise.
> > * config/arm/constraints.md (DB): Check for VALID_MVE_PRED_MODE
> > instead
> > of MODE_VECTOR_BOOL.
> > * config/arm/iterators.md (MVE_7, MVE_7_HI): Add V2QI
> > (MVE_VPRED): Likewise.
> > (MVE_vpred): Add V2QI and map upper case predicate modes to
> > lower case.
> > (MVE_vctp): New mode attribute.
> > (mode1): Remove.
> > (VCTPQ): Remove.
> > (VCTPQ_M): Remove.
> > * config/arm/mve.md (mve_vctp<mode1>qhi): Rename this...
> > (mve_vctp<MVE_vctp>q<MVE_vpred>): ... to this. And use new mode
> > attributes.
> > (mve_vpnothi): Rename this...
> > (mve_vpnotv16bi): ... to this.
> > (mve_vctp<mode1>q_mhi): Rename this...
> > (mve_vctp<MVE_vctp>q_m<MVE_vpred>):... to this.
> > (mve_vldrdq_gather_base_z_<supf>v2di,
> > mve_vldrdq_gather_offset_z_<supf>v2di,
> > mve_vldrdq_gather_shifted_offset_z_<supf>v2di,
> > mve_vstrdq_scatter_base_p_<supf>v2di,
> > mve_vstrdq_scatter_offset_p_<supf>v2di,
> > mve_vstrdq_scatter_offset_p_<supf>v2di_insn,
> > mve_vstrdq_scatter_shifted_offset_p_<supf>v2di,
> > mve_vstrdq_scatter_shifted_offset_p_<supf>v2di_insn,
> > mve_vstrdq_scatter_base_wb_p_<supf>v2di,
> > mve_vldrdq_gather_base_wb_z_<supf>v2di,
> > mve_vldrdq_gather_base_nowb_z_<supf>v2di,
> > mve_vldrdq_gather_base_wb_z_<supf>v2di_insn): Use V2QI insead of
> > HI for predicates.
> > * config/arm/unspecs.md (VCTP8Q, VCTP16Q, VCTP32Q, VCTP64Q):
> Replace
> > these...
> > (VCTP): ... with this.
> > (VCTP8Q_M, VCTP16Q_M, VCTP32Q_M, VCTP64Q_M): Replace these...
> > (VCTP_M): ... with this.
> > * config/arm/vfp.md (*thumb2_movhi_vfp, *thumb2_movhi_fp16): Use
> > VALID_MVE_PRED_MODE
> > instead of checking for MODE_VECTOR_BOOL class.
> >
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.dg/rtl/arm/mve-vxbi.c: Use new predicate modes.
> > * gcc.target/arm/mve/pr108443-run.c: New test.
> > * gcc.target/arm/mve/pr108443.c: New test.
diff --git a/gcc/testsuite/gcc.target/arm/mve/pr108443.c
b/gcc/testsuite/gcc.target/arm/mve/pr108443.c
new file mode 100644
index
0000000000000000000000000000000000000000..227d4b11f477a43b95ee981c190c289b84f1a486
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/mve/pr108443.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+#include <arm_mve.h>
+
+void
+__attribute__ ((noipa)) partial_write_cst (uint32_t *a, uint32x4_t v)
+{
+ vstrwq_p_u32 (a, v, 0x00CC);
+}
+
+/* { dg-final { scan-assembler {mov\tr[0-9][0-9]*, #204} } } */
+
The register scan can be a shorter "r[0-9]+".
Ok with that change. Please also double check the changelog entries to ensure
that they match what the committed version of the patch does.
Thanks for working on this!
Kyrill
