On 2/2/23 09:43, Robin Dapp wrote:
> Hi,
>
> this patch adds LEN_LOAD/LEN_STORE support for z14 and newer.
> It defines a bias value of -1 and implements the LEN_LOAD and LEN_STORE
> optabs.
>
> It also includes various vll/vstl testcases adapted from Kewen Lin's patch
> for Power.
>
> Bootstrapped and regtested on z13-z16.
>
> Is it OK?
>
> Regards
> Robin
>
> gcc/ChangeLog:
>
> * config/s390/predicates.md (vll_bias_operand): Add -1 bias.
> * config/s390/s390.cc (s390_option_override_internal): Make
> partial vector usage the default from z13 on.
> * config/s390/vector.md (len_load_v16qi): Add.
> (len_store_v16qi): Add.
...
> +;
> +; Implement len_load/len_store optabs with vll/vstl.
> +(define_expand "len_load_v16qi"
> + [(match_operand:V16QI 0 "register_operand")
> + (match_operand:V16QI 1 "memory_operand")
> + (match_operand:QI 2 "register_operand")
> + (match_operand:QI 3 "vll_bias_operand")
> + ]
> + "TARGET_VX && TARGET_64BIT"
> +{
> + rtx src1 = XEXP (operands[1], 0);
> + rtx src = gen_reg_rtx (Pmode);
> + emit_move_insn (src, src1);
> + rtx mem = gen_rtx_MEM (BLKmode, src);
Do you really need a copy of the address register? Couldn't you just do a
src = adjust_address (operands[1], BLKmode, 0);
> +
> + rtx len = gen_lowpart (SImode, operands[2]);
> + emit_insn (gen_vllv16qi (operands[0], len, mem));
You create a paradoxical subreg of the QImode input but vll actually uses the
whole 32 bit value.
Couldn't we end up with uninitialized bytes being used as part of the length
then? Do we need a
zero-extend here?
Bye,
Andreas
