[PATCH][committed] aarch64: Emit single-instruction for smin (x, 0) and smax (x, 0)

[Kyrylo Tkachov via Gcc-patches]

Hi all,

Motivated by https://reviews.llvm.org/D148249, we can expand to a single 
instruction
for the SMIN (x, 0) and SMAX (x, 0) cases using the combined AND/BIC and ASR 
operations.
Given that we already have well-fitting TARGET_CSSC patterns and expanders for 
the min/max codes
in the backend this patch does some minor refactoring to ensure we emit the 
right SMAX/SMIN RTL codes
for TARGET_CSSC, fall back to the generic expanders or emit a simple SMIN/SMAX 
with 0 RTX for !TARGET_CSSC
that is now matched by a separate pattern.

Bootstrapped and tested on aarch64-none-linux-gnu.

Pushing to trunk.
Thanks,
Kyrill

gcc/ChangeLog:

        * config/aarch64/aarch64.md (aarch64_umax<mode>3_insn): Delete.
        (umax<mode>3): Emit raw UMAX RTL instead of going through gen_ function
        for umax.
        (<optab><mode>3): New define_expand for MAXMIN_NOUMAX codes.
        (*aarch64_<optab><mode>3_zero): Define.
        (*aarch64_<optab><mode>3_cssc): Likewise.
        * config/aarch64/iterators.md (maxminand): New code attribute.

gcc/testsuite/ChangeLog:

        * gcc.target/aarch64/sminmax-asr_1.c: New test.

minmax.patch
Description: minmax.patch