On 2/10/23 15:41, Philipp Tomsich wrote:
Users might use explicit arithmetic operations to create a mask and
then and it, in a sequence like
cond = (bits >> SHIFT) & 1;
mask = ~(cond - 1);
val &= mask;
which will present as a single-bit sign-extract.
Dependening on what combination of XVentanaCondOps and Zbs are
available, this will map to the following sequences:
- bexti + czero, if both Zbs and XVentanaCondOps are present
- andi + czero, if only XVentanaCondOps is available and the
sign-extract is operating on bits 10:0 (bit 11
can't be reached, as the immediate is
sign-extended)
- slli + srli + and, otherwise.
gcc/ChangeLog:
* config/riscv/zicond.md: Recognize SIGN_EXTRACT of a
single-bit followed by AND for Zicond.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond-le-01.c: New test.
Conceptually OK. In fact using bext to drive if conversions is
something I think we've got in our queue of things to investigate here.
So you may have just made Raphael's work easier ;-)
As with the other patches we just need to adjust to using the
if-then-else form. You've got a mention of XVentanaCondOps in the
comments, you might want to change that to zicond.
jeff
