Thanks Kito for the better approach. It works well with the prepared test cases
but I may have one question about the semantics of the vector_move_operand.
The defined predicate of vector_move_operand composes of (non-imm || (const
vector && (reload_completed ? constraint_vi (op) : constraint_wc0(op))).
I may not quit understand why we group them together and named as vector_move.
Another difference is that it will act on combine pass which is more generic
than the PATCH v1 (which acts on split2 pass).
Pan
-----Original Message-----
From: Kito Cheng <kito.ch...@sifive.com>
Sent: Thursday, April 27, 2023 11:00 PM
To: Li, Pan2 <pan2...@intel.com>
Cc: gcc-patches@gcc.gnu.org; juzhe.zh...@rivai.ai; Wang, Yanzhang
<yanzhang.w...@intel.com>
Subject: Re: [PATCH] RISC-V: Allow RVV VMS{Compare}(V1, V1) simplify to VMCLR
> Could you try something like this? that should be more generic:
>
> (define_split
> [(set (match_operand:VB 0 "register_operand")
> (if_then_else:VB
> (unspec:VB
> [(match_operand:VB 1 "vector_all_trues_mask_operand")
> (match_operand 4 "vector_length_operand")
> (match_operand 5 "const_int_operand")
> (match_operand 6 "const_int_operand")
> (reg:SI VL_REGNUM)
> (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
> (match_operand:VB 3 "vector_move_operand")
> (match_operand:VB 2 "vector_undef_operand")))]
> "TARGET_VECTOR && reload_completed"
Remove the reload_completed should work well, but you might need more test, I
didn't run full test on this change :P
> [(const_int 0)]
> {
> emit_insn (gen_pred_mov (<MODE>mode, operands[0], CONST1_RTX (<MODE>mode),
> RVV_VUNDEF (<MODE>mode), CONST0_RTX (<MODE>mode),
> operands[4], operands[5]));
> DONE;
> }
> )
