On 4/28/23 10:56, Jeff Law wrote:
On 4/27/23 10:22, Patrick O'Neill wrote:
Introduce the %I and %J flags for setting the .aqrl bits on LR/SC pairs
as needed.
Atomic compare and exchange ops provide success and failure memory
models. C++17 and later place no restrictions on the relative strength
of each model, so ensure we cover both by using a model that enforces
the ordering of both given models.
This change brings LR/SC ops in line with table A.6 of the ISA manual.
2023-04-27 Patrick O'Neill <patr...@rivosinc.com>
gcc/ChangeLog:
* config/riscv/riscv-protos.h (riscv_union_memmodels): Expose
riscv_union_memmodels function to sync.md.
* config/riscv/riscv.cc (riscv_union_memmodels): Add function to
get the union of two memmodels in sync.md.
(riscv_print_operand): Add %I and %J flags that output the
optimal LR/SC flag bits for a given memory model.
* config/riscv/sync.md: Remove static .aqrl bits on LR op/.rl
bits on SC op and replace with optimized %I, %J flags.
OK.
Note for the future. Operands don't have to appear in-order in a
define_insn. So the kind of reordering you did here may not have been
strictly necessary. As you found out, when you renumber the
operands, you have to adjust the assembly template, which can be error
prone. Knowing that I checked them pretty closely and they look right
to me.
Jeff
Committed.
Patrick
