On Mon, 8 May 2023, Li, Pan2 wrote:
> return !dv || (int) GET_CODE ((rtx) dv) != (int) VALUE; } is able to fix
> this ICE after mode bits change.
Can you check which bits this will inspect when 'dv' is a tree after your
patch? VALUE is 1 and would map to IDENTIFIER_NODE on the tree side
when there was a 1:1 overlap.
I think for all cases but struct loc_exp_dep we could find a bit to
record wheter we deal with a VALUE or a decl, but for loc_exp_dep
it's going to be difficult (unless we start to take bits from
pointer representations).
That said, I agree with Jeff that the code is ugly, but a simplistic
conversion isn't what we want.
An alternative "solution" might be to also shrink tree_code when
we shrink rtx_code and keep the 1:1 overlap.
Richard.
> I will re-trigger the memory allocate
> bytes test with below changes for X86.
>
> rtx_def code 16 => 8 bits.
> rtx_def mode 8 => 16 bits.
> tree_base code unchanged.
>
> Pan
>
> -----Original Message-----
> From: Li, Pan2
> Sent: Monday, May 8, 2023 2:42 PM
> To: Richard Biener <rguent...@suse.de>; Jeff Law <jeffreya...@gmail.com>
> Cc: Kito Cheng <kito.ch...@gmail.com>; juzhe.zh...@rivai.ai;
> richard.sandiford <richard.sandif...@arm.com>; gcc-patches
> <gcc-patches@gcc.gnu.org>; palmer <pal...@dabbelt.com>; jakub
> <ja...@redhat.com>
> Subject: RE: [PATCH] machine_mode type size: Extend enum size from 8-bit to
> 16-bit
>
> Oops. Actually I am patching a version as you mentioned like storage
> allocation. Thank you Richard, will try your suggestion and keep you posted.
>
> Pan
>
> -----Original Message-----
> From: Richard Biener <rguent...@suse.de>
> Sent: Monday, May 8, 2023 2:30 PM
> To: Jeff Law <jeffreya...@gmail.com>
> Cc: Li, Pan2 <pan2...@intel.com>; Kito Cheng <kito.ch...@gmail.com>;
> juzhe.zh...@rivai.ai; richard.sandiford <richard.sandif...@arm.com>;
> gcc-patches <gcc-patches@gcc.gnu.org>; palmer <pal...@dabbelt.com>; jakub
> <ja...@redhat.com>
> Subject: Re: [PATCH] machine_mode type size: Extend enum size from 8-bit to
> 16-bit
>
> On Sun, 7 May 2023, Jeff Law wrote:
>
> >
> >
> > On 5/6/23 19:55, Li, Pan2 wrote:
> > > It looks like we cannot simply swap the code and mode in rtx_def,
> > > the code may have to be the same bits as the tree_code in tree_base.
> > > Or we will meet ICE like below.
> > >
> > > rtx_def code 16 => 8 bits.
> > > rtx_def mode 8 => 16 bits.
> > >
> > > static inline decl_or_value
> > > dv_from_value (rtx value)
> > > {
> > > decl_or_value dv;
> > > dv = value;
> > > gcc_checking_assert (dv_is_value_p (dv)); <= ICE
> > > return dv;
> > Ugh. We really just need to fix this code. It assumes particular
> > structure layouts and that's just wrong/dumb.
>
> Well, it's a neat trick ... we just need to adjust it to
>
> static inline bool
> dv_is_decl_p (decl_or_value dv)
> {
> return !dv || (int) GET_CODE ((rtx) dv) != (int) VALUE; }
>
> I think (and hope for the 'decl' case the bits inspected are never 'VALUE').
> Of course the above stinks from a TBAA perspective ...
>
> Any "real" fix would require allocating storage for a discriminator and thus
> hurt the resource constrained var-tracking a lot.
>
> Richard.
>
--
Richard Biener <rguent...@suse.de>
SUSE Software Solutions Germany GmbH, Frankenstrasse 146, 90461 Nuernberg,
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