Factorize vmladav, vmladavx, vmlsdav, vmlsdavx, vmladava, vmladavax,
vmlsdava, vmlsdavax builtins so that they use the same parameterized
names.
2022-10-25 Christophe Lyon <christophe.l...@arm.com>
gcc/
* config/arm/iterators.md (MVE_VMLxDAVQ, MVE_VMLxDAVQ_P)
(MVE_VMLxDAVAQ, MVE_VMLxDAVAQ_P): New.
(mve_insn): Add vmladava, vmladavax, vmladav, vmladavx, vmlsdava,
vmlsdavax, vmlsdav, vmlsdavx.
(supf): Add VMLADAVAXQ_P_S, VMLADAVAXQ_S, VMLADAVXQ_P_S,
VMLADAVXQ_S, VMLSDAVAQ_P_S, VMLSDAVAQ_S, VMLSDAVAXQ_P_S,
VMLSDAVAXQ_S, VMLSDAVQ_P_S, VMLSDAVQ_S, VMLSDAVXQ_P_S,
VMLSDAVXQ_S.
* config/arm/mve.md (mve_vmladavq_<supf><mode>)
(mve_vmladavxq_s<mode>, mve_vmlsdavq_s<mode>)
(mve_vmlsdavxq_s<mode>): Merge into ...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmlsdavaq_s<mode>, mve_vmladavaxq_s<mode>)
(mve_vmlsdavaxq_s<mode>, mve_vmladavaq_<supf><mode>): Merge into
...
(@mve_<mve_insn>q_<supf><mode>): ... this.
(mve_vmladavq_p_<supf><mode>, mve_vmladavxq_p_s<mode>)
(mve_vmlsdavq_p_s<mode>, mve_vmlsdavxq_p_s<mode>): Merge into ...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
(mve_vmladavaq_p_<supf><mode>, mve_vmladavaxq_p_s<mode>)
(mve_vmlsdavaq_p_s<mode>, mve_vmlsdavaxq_p_s<mode>): Merge into
...
(@mve_<mve_insn>q_p_<supf><mode>): ... this.
---
gcc/config/arm/iterators.md | 56 +++++++++
gcc/config/arm/mve.md | 236 +++++-------------------------------
2 files changed, 84 insertions(+), 208 deletions(-)
diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
index ff146afd913..68f5314041b 100644
--- a/gcc/config/arm/iterators.md
+++ b/gcc/config/arm/iterators.md
@@ -699,6 +699,34 @@ (define_int_iterator MVE_VMAXAVMINAQ_M [
VMINAQ_M_S
])
+(define_int_iterator MVE_VMLxDAVQ [
+ VMLADAVQ_S VMLADAVQ_U
+ VMLADAVXQ_S
+ VMLSDAVQ_S
+ VMLSDAVXQ_S
+ ])
+
+(define_int_iterator MVE_VMLxDAVQ_P [
+ VMLADAVQ_P_S VMLADAVQ_P_U
+ VMLADAVXQ_P_S
+ VMLSDAVQ_P_S
+ VMLSDAVXQ_P_S
+ ])
+
+(define_int_iterator MVE_VMLxDAVAQ [
+ VMLADAVAQ_S VMLADAVAQ_U
+ VMLSDAVAXQ_S
+ VMLSDAVAQ_S
+ VMLADAVAXQ_S
+ ])
+
+(define_int_iterator MVE_VMLxDAVAQ_P [
+ VMLADAVAQ_P_S VMLADAVAQ_P_U
+ VMLSDAVAXQ_P_S
+ VMLSDAVAQ_P_S
+ VMLADAVAXQ_P_S
+ ])
+
(define_int_iterator MVE_MOVN [
VMOVNBQ_S VMOVNBQ_U
VMOVNTQ_S VMOVNTQ_U
@@ -817,8 +845,24 @@ (define_int_attr mve_insn [
(VMINQ_M_S "vmin") (VMINQ_M_U "vmin")
(VMINVQ_P_S "vminv") (VMINVQ_P_U "vminv")
(VMINVQ_S "vminv") (VMINVQ_U "vminv")
+ (VMLADAVAQ_P_S "vmladava") (VMLADAVAQ_P_U "vmladava")
+ (VMLADAVAQ_S "vmladava") (VMLADAVAQ_U "vmladava")
+ (VMLADAVAXQ_P_S "vmladavax")
+ (VMLADAVAXQ_S "vmladavax")
+ (VMLADAVQ_P_S "vmladav") (VMLADAVQ_P_U "vmladav")
+ (VMLADAVQ_S "vmladav") (VMLADAVQ_U "vmladav")
+ (VMLADAVXQ_P_S "vmladavx")
+ (VMLADAVXQ_S "vmladavx")
(VMLAQ_M_N_S "vmla") (VMLAQ_M_N_U "vmla")
(VMLASQ_M_N_S "vmlas") (VMLASQ_M_N_U "vmlas")
+ (VMLSDAVAQ_P_S "vmlsdava")
+ (VMLSDAVAQ_S "vmlsdava")
+ (VMLSDAVAXQ_P_S "vmlsdavax")
+ (VMLSDAVAXQ_S "vmlsdavax")
+ (VMLSDAVQ_P_S "vmlsdav")
+ (VMLSDAVQ_S "vmlsdav")
+ (VMLSDAVXQ_P_S "vmlsdavx")
+ (VMLSDAVXQ_S "vmlsdavx")
(VMOVLBQ_M_S "vmovlb") (VMOVLBQ_M_U "vmovlb")
(VMOVLBQ_S "vmovlb") (VMOVLBQ_U "vmovlb")
(VMOVLTQ_M_S "vmovlt") (VMOVLTQ_M_U "vmovlt")
@@ -2237,6 +2281,18 @@ (define_int_attr supf [(VCVTQ_TO_F_S "s") (VCVTQ_TO_F_U
"u") (VREV16Q_S "s")
(VCMPLTQ_M_S "s")
(VCMPNEQ_M_N_S "s") (VCMPNEQ_M_N_U "u")
(VCMPNEQ_M_S "s") (VCMPNEQ_M_U "u")
+ (VMLADAVAXQ_P_S "s")
+ (VMLADAVAXQ_S "s")
+ (VMLADAVXQ_P_S "s")
+ (VMLADAVXQ_S "s")
+ (VMLSDAVAQ_P_S "s")
+ (VMLSDAVAQ_S "s")
+ (VMLSDAVAXQ_P_S "s")
+ (VMLSDAVAXQ_S "s")
+ (VMLSDAVQ_P_S "s")
+ (VMLSDAVQ_S "s")
+ (VMLSDAVXQ_P_S "s")
+ (VMLSDAVXQ_S "s")
])
;; Both kinds of return insn.
diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md
index b548eced4f5..f95525db583 100644
--- a/gcc/config/arm/mve.md
+++ b/gcc/config/arm/mve.md
@@ -985,62 +985,20 @@ (define_insn "@mve_<mve_insn>q_<supf><mode>"
])
;;
-;; [vmladavq_u, vmladavq_s])
+;; [vmladavq_u, vmladavq_s]
+;; [vmladavxq_s]
+;; [vmlsdavq_s]
+;; [vmlsdavxq_s]
;;
-(define_insn "mve_vmladavq_<supf><mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMLADAVQ))
- ]
- "TARGET_HAVE_MVE"
- "vmladav.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmladavxq_s])
-;;
-(define_insn "mve_vmladavxq_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMLADAVXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmladavx.s%#<V_sz_elem>\t%0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlsdavq_s])
-;;
-(define_insn "mve_vmlsdavq_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")]
- VMLSDAVQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmlsdav.s%#<V_sz_elem>\t%0, %q1, %q2"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlsdavxq_s])
-;;
-(define_insn "mve_vmlsdavxq_s<mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")]
- VMLSDAVXQ_S))
+ MVE_VMLxDAVQ))
]
"TARGET_HAVE_MVE"
- "vmlsdavx.s%#<V_sz_elem>\t%0, %q1, %q2"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
[(set_attr "type" "mve_move")
])
@@ -2043,50 +2001,40 @@ (define_insn "@mve_<mve_insn>q_p_<supf><mode>"
(set_attr "length""8")])
;;
-;; [vmladavaq_u, vmladavaq_s])
+;; [vmladavaq_u, vmladavaq_s]
+;; [vmladavaxq_s]
+;; [vmlsdavaq_s]
+;; [vmlsdavaxq_s]
;;
-(define_insn "mve_vmladavaq_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")]
- VMLADAVAQ))
+ MVE_VMLxDAVAQ))
]
"TARGET_HAVE_MVE"
- "vmladava.<supf>%#<V_sz_elem> %0, %q2, %q3"
+ "<mve_insn>.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
[(set_attr "type" "mve_move")
])
;;
-;; [vmladavq_p_u, vmladavq_p_s])
-;;
-(define_insn "mve_vmladavq_p_<supf><mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMLADAVQ_P))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmladavt.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmladavxq_p_s])
+;; [vmladavq_p_u, vmladavq_p_s]
+;; [vmladavxq_p_s]
+;; [vmlsdavq_p_s]
+;; [vmlsdavxq_p_s]
;;
-(define_insn "mve_vmladavxq_p_s<mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMLADAVXQ_P_S))
+ MVE_VMLxDAVQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vmladavxt.s%#<V_sz_elem>\t%0, %q1, %q2"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q1, %q2"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -2122,38 +2070,6 @@ (define_insn "mve_vmlasq_n_<supf><mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vmlsdavq_p_s])
-;;
-(define_insn "mve_vmlsdavq_p_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMLSDAVQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlsdavt.s%#<V_sz_elem> %0, %q1, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmlsdavxq_p_s])
-;;
-(define_insn "mve_vmlsdavxq_p_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:MVE_2 1 "s_register_operand" "w")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 3 "vpr_register_operand"
"Up")]
- VMLSDAVXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlsdavxt.s%#<V_sz_elem> %0, %q1, %q2"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmvnq_m_s, vmvnq_m_u])
;;
@@ -2460,54 +2376,6 @@ (define_insn "mve_vqdmladhq_s<mode>"
[(set_attr "type" "mve_move")
])
-;;
-;; [vmlsdavaxq_s])
-;;
-(define_insn "mve_vmlsdavaxq_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VMLSDAVAXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmlsdavax.s%#<V_sz_elem>\t%0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmlsdavaq_s])
-;;
-(define_insn "mve_vmlsdavaq_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VMLSDAVAQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmlsdava.s%#<V_sz_elem>\t%0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
-;;
-;; [vmladavaxq_s])
-;;
-(define_insn "mve_vmladavaxq_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")]
- VMLADAVAXQ_S))
- ]
- "TARGET_HAVE_MVE"
- "vmladavax.s%#<V_sz_elem>\t%0, %q2, %q3"
- [(set_attr "type" "mve_move")
-])
-
;;
;; [vabsq_m_f]
;; [vnegq_m_f]
@@ -3483,19 +3351,22 @@ (define_insn "@mve_<mve_insn>q_m_n_<supf><mode>"
;;
;;
-;; [vmladavaq_p_u, vmladavaq_p_s])
+;; [vmladavaq_p_u, vmladavaq_p_s]
+;; [vmladavaxq_p_s]
+;; [vmlsdavaq_p_s]
+;; [vmlsdavaxq_p_s]
;;
-(define_insn "mve_vmladavaq_p_<supf><mode>"
+(define_insn "@mve_<mve_insn>q_p_<supf><mode>"
[
(set (match_operand:SI 0 "s_register_operand" "=Te")
(unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
(match_operand:MVE_2 2 "s_register_operand" "w")
(match_operand:MVE_2 3 "s_register_operand" "w")
(match_operand:<MVE_VPRED> 4 "vpr_register_operand" "Up")]
- VMLADAVAQ_P))
+ MVE_VMLxDAVAQ_P))
]
"TARGET_HAVE_MVE"
- "vpst\;vmladavat.<supf>%#<V_sz_elem> %0, %q2, %q3"
+ "vpst\;<mve_insn>t.<supf>%#<V_sz_elem>\t%0, %q2, %q3"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
@@ -3637,57 +3508,6 @@ (define_insn "mve_vhcaddq_rot90_m_s<mode>"
[(set_attr "type" "mve_move")
(set_attr "length""8")])
-;;
-;; [vmladavaxq_p_s])
-;;
-(define_insn "mve_vmladavaxq_p_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLADAVAXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmladavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmlsdavaq_p_s])
-;;
-(define_insn "mve_vmlsdavaq_p_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLSDAVAQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlsdavat.s%#<V_sz_elem>\t%0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
-;;
-;; [vmlsdavaxq_p_s])
-;;
-(define_insn "mve_vmlsdavaxq_p_s<mode>"
- [
- (set (match_operand:SI 0 "s_register_operand" "=Te")
- (unspec:SI [(match_operand:SI 1 "s_register_operand" "0")
- (match_operand:MVE_2 2 "s_register_operand" "w")
- (match_operand:MVE_2 3 "s_register_operand" "w")
- (match_operand:<MVE_VPRED> 4 "vpr_register_operand"
"Up")]
- VMLSDAVAXQ_P_S))
- ]
- "TARGET_HAVE_MVE"
- "vpst\;vmlsdavaxt.s%#<V_sz_elem>\t%0, %q2, %q3"
- [(set_attr "type" "mve_move")
- (set_attr "length""8")])
-
;;
;; [vmlaldavaq_p_u, vmlaldavaq_p_s])
;;
--
2.34.1
