> +(define_expand "vec_cmp<mode><vm>"
> + [(set (match_operand:<VM> 0 "register_operand")
> + (match_operator:<VM> 1 "comparison_operator"
> + [(match_operand:VI 2 "register_operand")
> + (match_operand:VI 3 "register_operand")]))]
> + "TARGET_VECTOR"
> + {
> + riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
> + operands[2], operands[3]);
> + DONE;
> + }
> +)
> +
> +(define_expand "vec_cmpu<mode><vm>"
> + [(set (match_operand:<VM> 0 "register_operand")
> + (match_operator:<VM> 1 "comparison_operator"
> + [(match_operand:VI 2 "register_operand")
> + (match_operand:VI 3 "register_operand")]))]
> + "TARGET_VECTOR"
> + {
> + riscv_vector::expand_vec_cmp (operands[0], GET_CODE (operands[1]),
> + operands[2], operands[3]);
> + DONE;
> + }
> +)
> +
> +(define_expand "vec_cmp<mode><vm>"
> + [(set (match_operand:<VM> 0 "register_operand")
> + (match_operator:<VM> 1 "comparison_operator"
> + [(match_operand:VF 2 "register_operand")
> + (match_operand:VF 3 "register_operand")]))]
> + "TARGET_VECTOR"
> + {
> + riscv_vector::expand_vec_cmp_float (operands[0], GET_CODE (operands[1]),
> + operands[2], operands[3], false);
> + DONE;
> + }
> +)
Don't you want to use your shiny new operand passing style here as
with the other expanders?
> + /* We have a maximum of 11 operands for RVV instruction patterns according
> to
> + * vector.md. */
> + insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true,
> + /*FULLY_UNMASKED_P*/ false,
> + /*USE_REAL_MERGE_P*/ false, /*HAS_AVL_P*/ true,
> + /*VLMAX_P*/ true,
> + /*DEST_MODE*/ data_mode, /*MASK_MODE*/ mask_mode);
> + e.set_policy (TAIL_ANY);
> + e.emit_insn ((enum insn_code) icode, ops);
> +}
I don't think we need the same comment in each of these. Same for
/*DEST_MODE*/ and /*MASK_MODE*/ which would be redundant if data_mode
were called dest_mode.
> +/* Expand an RVV comparison. */
> +
> +void
> +expand_vec_cmp (rtx target, rtx_code code, rtx op0, rtx op1)
> +{
> + machine_mode mask_mode = GET_MODE (target);
> + machine_mode data_mode = GET_MODE (op0);
> + insn_code icode = get_cmp_insn_code (code, data_mode);
> +
> + if (code == LTGT)
> + {
> + rtx gt = gen_reg_rtx (mask_mode);
> + rtx lt = gen_reg_rtx (mask_mode);
> + expand_vec_cmp (gt, GT, op0, op1);
> + expand_vec_cmp (lt, LT, op0, op1);
> + icode = code_for_pred (IOR, mask_mode);
> + rtx ops[3] = {target, gt, lt};
> + emit_vlmax_insn (icode, riscv_vector::RVV_BINOP, ops);
> + return;
> + }
Swap lt and gt here for consistency's sake.
Regards
Robin
