Re: Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

[juzhe.zh...@rivai.ai]

>> Yeah sure, we need to be able to run tests only for specific targets.
>> Why does {riscv_vector} && {rv64} not work?
I am not sure. These testcases were added by kito long time ago.
Frankly, I am not familiar with GCC test framework.

I think the highest priority is to fix the "real" compiler bugs which I have 
noticed yesterday:
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/partial/multiple_rgroup_run-2.c execution 
test
FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/repeat_run-3.c -std=c99 -O3 
-ftree-vectorize --param riscv-autovec-preference=fixed-vlmax execution test

@Li Pan could you verify whether your patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-June/621610.html can fix these 2 
issues?
If yes, please send V2 patch with append these information into patch log.


Thanks.


juzhe.zh...@rivai.ai
 
From: Robin Dapp
Date: 2023-06-14 14:52
To: juzhe.zh...@rivai.ai; pan2.li; gcc-patches
CC: rdapp.gcc; jeffreyalaw; yanzhang.wang; kito.cheng
Subject: Re: [PATCH v1] RISC-V: Align the predictor style for 
define_insn_and_split
Yes, I agree with the general assessment (and didn't mean to insinuate
that the FAILs are compiler's or a fault of the patch.
 
> So these 2 failures in RV32 are not the compile's bugs. I have seen:
> /* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ in
> these testcases which can not work to block execution in RV32 (Since
> such testcase only needs to be tested on RV64). I think this is the
> issue we need to figure out.
 
Yeah sure, we need to be able to run tests only for specific targets.
Why does {riscv_vector} && {rv64} not work?
 
For zvfh I'm testing something like the following:
 
proc check_effective_target_riscv_zvfh { } {
    if { ![istarget rv32*-*-*] && ![istarget rv64*-*-*] } then {
return 0;
    }
 
    if !check_effective_target_riscv_vector then {
return 0;
    }
 
    return [
[check_runtime riscv_check_zvfh {
    int main (void)
    {
asm ("vsetivli zero,8,e16,m1,ta,ma");
asm ("vfadd.vv %%v8,%%v8,%%v16" : : : "%%v8");
return 0;
    }
} "-march=rv64gcv_zvfh" ]
|| ... ]
 
Regards
Robin