Hi Juzhe, > +@cindex @code{len_maskload@var{m}@var{n}} instruction pattern > +@item @samp{len_maskload@var{m}@var{n}} > +Perform a masked load (operand 2 - operand 4) elements from vector memory > +operand 1 into vector register operand 0, setting the other elements of > +operand 0 to undefined values. This is a combination of len_load and > maskload. > +Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 2 > +has whichever integer mode the target prefers. A secondary mask is > specified in > +operand 3 which must be of type @var{n}. Operand 4 conceptually has mode > @code{QI}. > + > +Operand 2 can be a variable or a constant amount. Operand 4 specifies a > +constant bias: it is either a constant 0 or a constant -1. The predicate on > +operand 4 must only accept the bias values that the target actually supports. > +GCC handles a bias of 0 more efficiently than a bias of -1. > + > +If (operand 2 - operand 4) exceeds the number of elements in mode > +@var{m}, the behavior is undefined. > + > +If the target prefers the length to be measured in bytes > +rather than elements, it should only implement this pattern for vectors > +of @code{QI} elements. > + > +This pattern is not allowed to @code{FAIL}.
Please still change "Perform a masked load (operand 2 - operand 4) elements" to "Perform a masked load of (operand 2 + operand 4) elements". "vector memory operand" -> "memory operand" As Richi has mentioned we are adding the negative bias not subtracting a positive one. You could also change the len_load and len_store comments while at it so as to not introduce more confusion. The "secondary" can also be omitted now because we don't have a primary mask somewhere. Maybe, for clarification, even if it's implicit: "A mask is specified in operand 3 which must... The mask has lower precedence than the length and is itself subject to length masking, i.e. only mask indices <= (operand 2 + operand 4) are used." > + > +@cindex @code{len_maskstore@var{m}@var{n}} instruction pattern > +@item @samp{len_maskstore@var{m}@var{n}} > +Perform a masked store (operand 2 - operand 4) vector elements from vector > register > +operand 1 into memory operand 0, leaving the other elements of operand 0 > unchanged. > +This is a combination of len_store and maskstore. > +Operands 0 and 1 have mode @var{m}, which must be a vector mode. Operand 2 > has whichever > +integer mode the target prefers. A secondary mask is specified in operand 3 > which must be > +of type @var{n}. Operand 4 conceptually has mode @code{QI}. Same thing applies here "store of (operand 2 + operand 4) vector elements as well as the secondary. Thanks. No V5 necessary IMHO for those but let's see what Richard says. Regards Robin