Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

[Robin Dapp via Gcc-patches]

Hi Juzhe,

> Currently, we are able to generate step vector with base == 0:
>  { 0, 0, 2, 2, 4, 4, ... }
> 
> ASM:
> 
> vid
> vand
> 
> However, we do wrong for step vector with base != 0:
> { 1, 1, 3, 3, 5, 5, ... }
> 
> Before this patch, such case will run fail.
> 
> After this patch, we are able to pass the testcase and generate the step 
> vector with asm:
> 
> vid
> vand
> vadd

Can't we use the first case as long as pow2_p (base) == true
and not just for base == 0?

Regards
 Robin