LGTM, thanks for the patch :)
On Mon, Jul 17, 2023 at 5:53 PM Lehua Ding <lehua.d...@rivai.ai> wrote:
>
> Hi,
>
> This patch fix target/PR110696, recursively add all implied extensions.
>
> Best,
> Lehua
>
> PR target/110696
>
> gcc/ChangeLog:
>
> * common/config/riscv/riscv-common.cc
> (riscv_subset_list::handle_implied_ext): recur add all implied extensions.
> (riscv_subset_list::check_implied_ext): Add new method.
> (riscv_subset_list::parse): Call checker check_implied_ext.
> * config/riscv/riscv-subset.h: Add new method.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/attribute-20.c: New test.
> * gcc.target/riscv/pr110696.c: New test.
>
> ---
> gcc/common/config/riscv/riscv-common.cc | 33 +++++++++++++++++--
> gcc/config/riscv/riscv-subset.h | 3 +-
> gcc/testsuite/gcc.target/riscv/attribute-20.c | 7 ++++
> gcc/testsuite/gcc.target/riscv/pr110696.c | 7 ++++
> 4 files changed, 46 insertions(+), 4 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/riscv/attribute-20.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/pr110696.c
>
> diff --git a/gcc/common/config/riscv/riscv-common.cc
> b/gcc/common/config/riscv/riscv-common.cc
> index 28c8f0c1489..19075c0b241 100644
> --- a/gcc/common/config/riscv/riscv-common.cc
> +++ b/gcc/common/config/riscv/riscv-common.cc
> @@ -949,14 +949,14 @@ riscv_subset_list::parse_std_ext (const char *p)
>
> /* Check any implied extensions for EXT. */
> void
> -riscv_subset_list::handle_implied_ext (riscv_subset_t *ext)
> +riscv_subset_list::handle_implied_ext (const char *ext)
> {
> const riscv_implied_info_t *implied_info;
> for (implied_info = &riscv_implied_info[0];
> implied_info->ext;
> ++implied_info)
> {
> - if (strcmp (ext->name.c_str (), implied_info->ext) != 0)
> + if (strcmp (ext, implied_info->ext) != 0)
> continue;
>
> /* Skip if implied extension already present. */
> @@ -966,6 +966,9 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t
> *ext)
> /* Version of implied extension will get from current ISA spec
> version. */
> add (implied_info->implied_ext, true);
> +
> + /* Recursively add implied extension by implied_info->implied_ext. */
> + handle_implied_ext (implied_info->implied_ext);
> }
>
> /* For RISC-V ISA version 2.2 or earlier version, zicsr and zifence is
> @@ -980,6 +983,27 @@ riscv_subset_list::handle_implied_ext (riscv_subset_t
> *ext)
> }
> }
>
> +/* Check that all implied extensions are included. */
> +bool
> +riscv_subset_list::check_implied_ext ()
> +{
> + riscv_subset_t *itr;
> + for (itr = m_head; itr != NULL; itr = itr->next)
> + {
> + const riscv_implied_info_t *implied_info;
> + for (implied_info = &riscv_implied_info[0]; implied_info->ext;
> + ++implied_info)
> + {
> + if (strcmp (itr->name.c_str(), implied_info->ext) != 0)
> + continue;
> +
> + if (!lookup (implied_info->implied_ext))
> + return false;
> + }
> + }
> + return true;
> +}
> +
> /* Check any combine extensions for EXT. */
> void
> riscv_subset_list::handle_combine_ext ()
> @@ -1194,9 +1218,12 @@ riscv_subset_list::parse (const char *arch, location_t
> loc)
>
> for (itr = subset_list->m_head; itr != NULL; itr = itr->next)
> {
> - subset_list->handle_implied_ext (itr);
> + subset_list->handle_implied_ext (itr->name.c_str ());
> }
>
> + /* Make sure all implied extensions are included. */
> + gcc_assert (subset_list->check_implied_ext ());
> +
> subset_list->handle_combine_ext ();
>
> if (subset_list->lookup ("zfinx") && subset_list->lookup ("f"))
> diff --git a/gcc/config/riscv/riscv-subset.h b/gcc/config/riscv/riscv-subset.h
> index 92e4fb31692..84a7a82db63 100644
> --- a/gcc/config/riscv/riscv-subset.h
> +++ b/gcc/config/riscv/riscv-subset.h
> @@ -67,7 +67,8 @@ private:
> const char *parse_multiletter_ext (const char *, const char *,
> const char *);
>
> - void handle_implied_ext (riscv_subset_t *);
> + void handle_implied_ext (const char *);
> + bool check_implied_ext ();
> void handle_combine_ext ();
>
> public:
> diff --git a/gcc/testsuite/gcc.target/riscv/attribute-20.c
> b/gcc/testsuite/gcc.target/riscv/attribute-20.c
> new file mode 100644
> index 00000000000..f7d0b29b71c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/attribute-20.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl65536b -mabi=lp64d" } */
> +int foo()
> +{
> +}
> +
> +/* { dg-final { scan-assembler ".attribute arch,
> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl16384b1p0_zvl2048b1p0_zvl256b1p0_zvl32768b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0_zvl65536b1p0_zvl8192b1p0\""
> } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/pr110696.c
> b/gcc/testsuite/gcc.target/riscv/pr110696.c
> new file mode 100644
> index 00000000000..a630f04e74f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/pr110696.c
> @@ -0,0 +1,7 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvl4096b -mabi=lp64d" } */
> +int foo()
> +{
> +}
> +
> +/* { dg-final { scan-assembler ".attribute arch,
> \"rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zicsr2p0_zifencei2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl1024b1p0_zvl128b1p0_zvl2048b1p0_zvl256b1p0_zvl32b1p0_zvl4096b1p0_zvl512b1p0_zvl64b1p0\""
> } } */
> --
> 2.36.3
>
