lgtm
On Wed, Aug 16, 2023 at 2:51 PM <pan2...@intel.com> wrote:
> From: Pan Li <pan2...@intel.com>
>
> This patch would like to support the rounding mode API for the
> VFCVT.F.X.V and VFCVT.F.XU.V as the below samples.
>
> * __riscv_vfcvt_f_x_v_f32m1_rm
> * __riscv_vfcvt_f_x_v_f32m1_rm_m
> * __riscv_vfcvt_f_xu_v_f32m1_rm
> * __riscv_vfcvt_f_xu_v_f32m1_rm_m
>
> Signed-off-by: Pan Li <pan2...@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-bases.cc (BASE): New
> declaration.
> * config/riscv/riscv-vector-builtins-bases.h: Ditto.
> * config/riscv/riscv-vector-builtins-functions.def
> (vfcvt_f_frm): New intrinsic function def.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/base/float-point-cvt-f.c: New test.
> ---
> .../riscv/riscv-vector-builtins-bases.cc | 8 +++
> .../riscv/riscv-vector-builtins-bases.h | 1 +
> .../riscv/riscv-vector-builtins-functions.def | 2 +
> .../riscv/rvv/base/float-point-cvt-f.c | 50 +++++++++++++++++++
> 4 files changed, 61 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> index 421f4096db8..c78fa8e5b62 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
> @@ -1694,9 +1694,15 @@ public:
> }
> };
>
> +template<enum frm_op_type FRM_OP = NO_FRM>
> class vfcvt_f : public function_base
> {
> public:
> + bool has_rounding_mode_operand_p () const override
> + {
> + return FRM_OP == HAS_FRM;
> + }
> +
> rtx expand (function_expander &e) const override
> {
> if (e.op_info->op == OP_TYPE_x_v)
> @@ -2482,6 +2488,7 @@ static CONSTEXPR const
> vfcvt_x<UNSPEC_UNSIGNED_VFCVT, HAS_FRM> vfcvt_xu_frm_obj;
> static CONSTEXPR const vfcvt_rtz_x<FIX> vfcvt_rtz_x_obj;
> static CONSTEXPR const vfcvt_rtz_x<UNSIGNED_FIX> vfcvt_rtz_xu_obj;
> static CONSTEXPR const vfcvt_f vfcvt_f_obj;
> +static CONSTEXPR const vfcvt_f<HAS_FRM> vfcvt_f_frm_obj;
> static CONSTEXPR const vfwcvt_x<UNSPEC_VFCVT> vfwcvt_x_obj;
> static CONSTEXPR const vfwcvt_x<UNSPEC_UNSIGNED_VFCVT> vfwcvt_xu_obj;
> static CONSTEXPR const vfwcvt_rtz_x<FIX> vfwcvt_rtz_x_obj;
> @@ -2733,6 +2740,7 @@ BASE (vfcvt_xu_frm)
> BASE (vfcvt_rtz_x)
> BASE (vfcvt_rtz_xu)
> BASE (vfcvt_f)
> +BASE (vfcvt_f_frm)
> BASE (vfwcvt_x)
> BASE (vfwcvt_xu)
> BASE (vfwcvt_rtz_x)
> diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.h
> b/gcc/config/riscv/riscv-vector-builtins-bases.h
> index 98b61655692..08452587180 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-bases.h
> +++ b/gcc/config/riscv/riscv-vector-builtins-bases.h
> @@ -211,6 +211,7 @@ extern const function_base *const vfcvt_xu_frm;
> extern const function_base *const vfcvt_rtz_x;
> extern const function_base *const vfcvt_rtz_xu;
> extern const function_base *const vfcvt_f;
> +extern const function_base *const vfcvt_f_frm;
> extern const function_base *const vfwcvt_x;
> extern const function_base *const vfwcvt_xu;
> extern const function_base *const vfwcvt_rtz_x;
> diff --git a/gcc/config/riscv/riscv-vector-builtins-functions.def
> b/gcc/config/riscv/riscv-vector-builtins-functions.def
> index 613bbe7a855..8dbcd946d11 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-functions.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-functions.def
> @@ -447,6 +447,8 @@ DEF_RVV_FUNCTION (vfcvt_f, alu, full_preds,
> u_to_f_xu_v_ops)
>
> DEF_RVV_FUNCTION (vfcvt_x_frm, alu_frm, full_preds, f_to_i_f_v_ops)
> DEF_RVV_FUNCTION (vfcvt_xu_frm, alu_frm, full_preds, f_to_u_f_v_ops)
> +DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, i_to_f_x_v_ops)
> +DEF_RVV_FUNCTION (vfcvt_f_frm, alu_frm, full_preds, u_to_f_xu_v_ops)
>
> // 13.18. Widening Floating-Point/Integer Type-Convert Instructions
> DEF_RVV_FUNCTION (vfwcvt_x, alu, full_preds, f_to_wi_f_v_ops)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
> b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
> new file mode 100644
> index 00000000000..424a38ede13
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-cvt-f.c
> @@ -0,0 +1,50 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +vfloat32m1_t
> +test_riscv_vfcvt_f_x_v_f32m1_rm (vint32m1_t op1, size_t vl) {
> + return __riscv_vfcvt_f_x_v_f32m1_rm (op1, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfcvt_f_x_v_f32m1_rm_m (vbool32_t mask, vint32m1_t op1, size_t
> vl) {
> + return __riscv_vfcvt_f_x_v_f32m1_rm_m (mask, op1, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfcvt_f_xu_v_f32m1_rm (vuint32m1_t op1, size_t vl) {
> + return __riscv_vfcvt_f_xu_v_f32m1_rm (op1, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfcvt_f_xu_v_f32m1_rm_m (vbool32_t mask, vuint32m1_t op1,
> + size_t vl) {
> + return __riscv_vfcvt_f_xu_v_f32m1_rm_m (mask, op1, 0, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfcvt_f_x_v_f32m1 (vint32m1_t op1, size_t vl) {
> + return __riscv_vfcvt_f_x_v_f32m1 (op1, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfcvt_f_x_v_f32m1_m (vbool32_t mask, vint32m1_t op1, size_t vl) {
> + return __riscv_vfcvt_f_x_v_f32m1_m (mask, op1, vl);
> +}
> +
> +vfloat32m1_t
> +test_riscv_vfcvt_f_xu_v_f32m1 (vuint32m1_t op1, size_t vl) {
> + return __riscv_vfcvt_f_xu_v_f32m1 (op1, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfcvt_f_x_vu_f32m1_m (vbool32_t mask, vuint32m1_t op1, size_t vl) {
> + return __riscv_vfcvt_f_xu_v_f32m1_m (mask, op1, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vfcvt\.f\.x[u]?\.v\s+v[0-9]+,\s*v[0-9]+} 8 } } */
> +/* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 4 } } */
> --
> 2.34.1
>
>
