From: Kong Lingling <lingling.k...@intel.com>
For APX, as we extended the GENERAL_REG_CLASS, new constraints are
needed to restrict insns that cannot adopt EGPR either in its reg or
memory operands.
gcc/ChangeLog:
* config/i386/constraints.md (h): New register constraint
for GENERAL_GPR16.
(Bt): New non-EGPR memory constraint.
(BT): Likewise for Bm constraint.
* config/i386/i386.h (enum reg_class): Add new reg class
GENERAL_GPR16.
---
gcc/config/i386/constraints.md | 19 ++++++++++++++++++-
gcc/config/i386/i386.h | 4 ++++
2 files changed, 22 insertions(+), 1 deletion(-)
diff --git a/gcc/config/i386/constraints.md b/gcc/config/i386/constraints.md
index fd490f39110..f487bf2e5a3 100644
--- a/gcc/config/i386/constraints.md
+++ b/gcc/config/i386/constraints.md
@@ -19,7 +19,7 @@
;;; Unused letters:
;;; H
-;;; h j z
+;;; j z
;; Integer register constraints.
;; It is not necessary to define 'r' here.
@@ -165,6 +165,8 @@ (define_register_constraint "YW"
;; k TLS address that allows insn using non-integer registers
;; n Memory operand without REX prefix
;; r Broadcast memory operand
+;; t Memory operand without EGPR
+;; T Vector memory operand without EGPR
;; s Sibcall memory operand, not valid for TARGET_X32
;; w Call memory operand, not valid for TARGET_X32
;; z Constant call address operand.
@@ -201,6 +203,18 @@ (define_special_memory_constraint "Bn"
"@internal Memory operand without REX prefix."
(match_operand 0 "norex_memory_operand"))
+(define_memory_constraint "Bt"
+ "@internal Memory operand without GPR32."
+ (and (match_operand 0 "memory_operand")
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
+(define_special_memory_constraint "BT"
+ "@internal vector memory operand without GPR32."
+ (and (match_operand 0 "vector_memory_operand")
+ (not (and (match_test "TARGET_APX_EGPR")
+ (match_test "x86_extended_rex2reg_mentioned_p (op)")))))
+
(define_special_memory_constraint "Br"
"@internal bcst memory operand."
(match_operand 0 "bcst_mem_operand"))
@@ -371,3 +385,6 @@ (define_address_constraint "Tv"
(define_address_constraint "Ts"
"Address operand without segment register"
(match_operand 0 "address_no_seg_operand"))
+
+(define_register_constraint "h"
+ "TARGET_APX_EGPR ? GENERAL_GPR16 : GENERAL_REGS")
diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index 1ab291177f5..7ec3086641c 100644
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -1295,6 +1295,8 @@ enum reg_class
%r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15
%r16 %r17 %r18 %r19 %r20 %r21 %r22 %r23
%r24 %r25 %r26 %r27 %r28 %r29 %r30 %r31 */
+ GENERAL_GPR16, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp
+ %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */
FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */
FLOAT_REGS,
SSE_FIRST_REG,
@@ -1357,6 +1359,7 @@ enum reg_class
"INDEX_REGS", \
"LEGACY_REGS", \
"GENERAL_REGS", \
+ "GENERAL_GPR16", \
"FP_TOP_REG", "FP_SECOND_REG", \
"FLOAT_REGS", \
"SSE_FIRST_REG", \
@@ -1395,6 +1398,7 @@ enum reg_class
{ 0x7f, 0xff0, 0x0 }, /* INDEX_REGS */ \
{ 0x900ff, 0x0, 0x0 }, /* LEGACY_REGS */ \
{ 0x900ff, 0xff0, 0xffff000 }, /* GENERAL_REGS */
\
+ { 0x900ff, 0xff0, 0x0 }, /* GENERAL_GPR16 */ \
{ 0x100, 0x0, 0x0 }, /* FP_TOP_REG */ \
{ 0x200, 0x0, 0x0 }, /* FP_SECOND_REG */ \
{ 0xff00, 0x0, 0x0 }, /* FLOAT_REGS */ \
--
2.31.1
