LGTM
On Mon, Sep 4, 2023 at 3:18 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2...@intel.com>
>
> This patch would like to add FP16 support for the VRGATHEREI16
> intrinsic. Aka:
>
> * __riscv_vrgatherei16_vv_f16mf4
> * __riscv_vrgatherei16_vv_f16mf4_m
>
> As well as f16mf2 to f16m8 types.
>
> Signed-off-by: Pan Li <pan2...@intel.com>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv-vector-builtins-types.def
> (vfloat16mf4_t): Add FP16 intrinsic def.
> (vfloat16mf2_t): Ditto.
> (vfloat16m1_t): Ditto.
> (vfloat16m2_t): Ditto.
> (vfloat16m4_t): Ditto.
> (vfloat16m8_t): Ditto.
>
> gcc/testsuite/ChangeLog:
>
> * gcc.target/riscv/rvv/intrisinc-vrgatherei16.c: New test.
> ---
> .../riscv/riscv-vector-builtins-types.def | 9 ++++++
> .../riscv/rvv/intrisinc-vrgatherei16.c | 28 +++++++++++++++++++
> 2 files changed, 37 insertions(+)
> create mode 100644
> gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
>
> diff --git a/gcc/config/riscv/riscv-vector-builtins-types.def
> b/gcc/config/riscv/riscv-vector-builtins-types.def
> index 1c3cc0eb222..6aa45ae9a7e 100644
> --- a/gcc/config/riscv/riscv-vector-builtins-types.def
> +++ b/gcc/config/riscv/riscv-vector-builtins-types.def
> @@ -689,11 +689,20 @@ DEF_RVV_EI16_OPS (vuint64m1_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_EI16_OPS (vuint64m2_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_EI16_OPS (vuint64m4_t, RVV_REQUIRE_ELEN_64)
> DEF_RVV_EI16_OPS (vuint64m8_t, RVV_REQUIRE_ELEN_64)
> +
> +DEF_RVV_EI16_OPS (vfloat16mf4_t, RVV_REQUIRE_ELEN_FP_16 |
> RVV_REQUIRE_MIN_VLEN_64)
> +DEF_RVV_EI16_OPS (vfloat16mf2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m1_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m2_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m4_t, RVV_REQUIRE_ELEN_FP_16)
> +DEF_RVV_EI16_OPS (vfloat16m8_t, RVV_REQUIRE_ELEN_FP_16)
> +
> DEF_RVV_EI16_OPS (vfloat32mf2_t, RVV_REQUIRE_ELEN_FP_32 |
> RVV_REQUIRE_MIN_VLEN_64)
> DEF_RVV_EI16_OPS (vfloat32m1_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_EI16_OPS (vfloat32m2_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_EI16_OPS (vfloat32m4_t, RVV_REQUIRE_ELEN_FP_32)
> DEF_RVV_EI16_OPS (vfloat32m8_t, RVV_REQUIRE_ELEN_FP_32)
> +
> DEF_RVV_EI16_OPS (vfloat64m1_t, RVV_REQUIRE_ELEN_FP_64)
> DEF_RVV_EI16_OPS (vfloat64m2_t, RVV_REQUIRE_ELEN_FP_64)
> DEF_RVV_EI16_OPS (vfloat64m4_t, RVV_REQUIRE_ELEN_FP_64)
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
> b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
> new file mode 100644
> index 00000000000..59c6d7c887d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/intrisinc-vrgatherei16.c
> @@ -0,0 +1,28 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef _Float16 float16_t;
> +
> +vfloat16mf4_t test_vrgatherei16_vv_f16mf4(vfloat16mf4_t op1, vuint16mf4_t
> op2,
> + size_t vl) {
> + return __riscv_vrgatherei16_vv_f16mf4(op1, op2, vl);
> +}
> +
> +vfloat16m8_t test_vrgatherei16_vv_f16m8(vfloat16m8_t op1, vuint16m8_t op2,
> + size_t vl) {
> + return __riscv_vrgatherei16_vv_f16m8(op1, op2, vl);
> +}
> +
> +vfloat16mf4_t test_vrgatherei16_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t
> op1,
> + vuint16mf4_t op2, size_t vl) {
> + return __riscv_vrgatherei16_vv_f16mf4_m(mask, op1, op2, vl);
> +}
> +
> +vfloat16m8_t test_vrgatherei16_vv_f16m8_m(vbool2_t mask, vfloat16m8_t op1,
> + vuint16m8_t op2, size_t vl) {
> + return __riscv_vrgatherei16_vv_f16m8_m(mask, op1, op2, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times
> {vrgatherei16.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 4 } } */
> --
> 2.34.1
>
