Committed, thanks Juzhe. Pan
From: juzhe.zh...@rivai.ai <juzhe.zh...@rivai.ai> Sent: Tuesday, September 5, 2023 7:14 PM To: Li, Pan2 <pan2...@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org> Cc: Li, Pan2 <pan2...@intel.com>; Wang, Yanzhang <yanzhang.w...@intel.com>; kito.cheng <kito.ch...@gmail.com> Subject: Re: [PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode LGTM ________________________________ juzhe.zh...@rivai.ai<mailto:juzhe.zh...@rivai.ai> From: pan2.li<mailto:pan2...@intel.com> Date: 2023-09-05 18:32 To: gcc-patches<mailto:gcc-patches@gcc.gnu.org> CC: juzhe.zhong<mailto:juzhe.zh...@rivai.ai>; pan2.li<mailto:pan2...@intel.com>; yanzhang.wang<mailto:yanzhang.w...@intel.com>; kito.cheng<mailto:kito.ch...@gmail.com> Subject: [PATCH v1] RISC-V: Support FP SGNJ autovec for VLS mode From: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> This patch would like to allow the VLS mode autovec for the floating-point binary operation MAX/MIN. Given below code example: void test(float * restrict out, float * restrict in1, float * restrict in2) { for (int i = 0; i < 128; i++) out[i] = __builtin_copysignf (in1[i], in2[i]); } Before this patch: test: csrr a4,vlenb slli a4,a4,1 li a5,128 bleu a5,a4,.L2 mv a5,a4 .L2: vsetvli zero,a5,e32,m8,ta,ma vle32.v v8,0(a1) vle32.v v16,0(a2) vsetvli a4,zero,e32,m8,ta,ma vfsgnj.vv v8,v8,v16 vsetvli zero,a5,e32,m8,ta,ma vse32.v v8,0(a0) ret After this patch: test: li a5,128 vsetvli zero,a5,e32,m1,ta,ma vle32.v v1,0(a1) vle32.v v2,0(a2) vfsgnj.vv v1,v1,v2 vse32.v v1,0(a0) ret Signed-off-by: Pan Li <pan2...@intel.com<mailto:pan2...@intel.com>> gcc/ChangeLog: * config/riscv/autovec-vls.md (copysign<mode>3): New pattern. * config/riscv/vector.md: Extend iterator for VLS. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/vls/def.h: New macro. * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c: New test. * gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c: New test. --- gcc/config/riscv/autovec-vls.md | 22 ++++++++++ gcc/config/riscv/vector.md | 24 +++++------ .../gcc.target/riscv/rvv/autovec/vls/def.h | 8 ++++ .../rvv/autovec/vls/floating-point-sgnj-1.c | 43 +++++++++++++++++++ .../rvv/autovec/vls/floating-point-sgnj-2.c | 43 +++++++++++++++++++ 5 files changed, 128 insertions(+), 12 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c diff --git a/gcc/config/riscv/autovec-vls.md b/gcc/config/riscv/autovec-vls.md index 7ef29637e33..31b6c4ae714 100644 --- a/gcc/config/riscv/autovec-vls.md +++ b/gcc/config/riscv/autovec-vls.md @@ -255,6 +255,28 @@ (define_insn_and_split "<optab><mode>3" [(set_attr "type" "vector")] ) +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfsgnj.vv +;; - vfsgnj.vf +;; ------------------------------------------------------------------------- +(define_insn_and_split "copysign<mode>3" + [(set (match_operand:VLSF 0 "register_operand") + (unspec:VLSF + [(match_operand:VLSF 1 "register_operand") + (match_operand:VLSF 2 "register_operand")] UNSPEC_VCOPYSIGN))] + "TARGET_VECTOR && can_create_pseudo_p ()" + "#" + "&& 1" + [(const_int 0)] + { + riscv_vector::emit_vlmax_insn (code_for_pred (UNSPEC_VCOPYSIGN, <MODE>mode), + riscv_vector::BINARY_OP, operands); + DONE; + } + [(set_attr "type" "vector")] +) + ;; ------------------------------------------------------------------------------- ;; ---- [INT] Unary operations ;; ------------------------------------------------------------------------------- diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 9d7b4bbe1d4..fc985ff6a01 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -6166,8 +6166,8 @@ (define_insn "@pred_<optab><mode>_reverse_scalar" (symbol_ref "riscv_vector::get_frm_mode (operands[9])"))]) (define_insn "@pred_<copysign><mode>" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec:<VM> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6176,10 +6176,10 @@ (define_insn "@pred_<copysign><mode>" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (unspec:VF - [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") - (match_operand:VF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (unspec:V_VLSF + [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr") + (match_operand:V_VLSF 4 "register_operand" " vr, vr, vr, vr")] VCOPYSIGNS) + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfsgnj<nx>.vv\t%0,%3,%4%p1" [(set_attr "type" "vfsgnj") @@ -6207,8 +6207,8 @@ (define_insn "@pred_ncopysign<mode>" (set_attr "mode" "<MODE>")]) (define_insn "@pred_<copysign><mode>_scalar" - [(set (match_operand:VF 0 "register_operand" "=vd, vd, vr, vr") - (if_then_else:VF + [(set (match_operand:V_VLSF 0 "register_operand" "=vd, vd, vr, vr") + (if_then_else:V_VLSF (unspec:<VM> [(match_operand:<VM> 1 "vector_mask_operand" " vm, vm,Wc1,Wc1") (match_operand 5 "vector_length_operand" " rK, rK, rK, rK") @@ -6217,11 +6217,11 @@ (define_insn "@pred_<copysign><mode>_scalar" (match_operand 8 "const_int_operand" " i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) - (unspec:VF - [(match_operand:VF 3 "register_operand" " vr, vr, vr, vr") - (vec_duplicate:VF + (unspec:V_VLSF + [(match_operand:V_VLSF 3 "register_operand" " vr, vr, vr, vr") + (vec_duplicate:V_VLSF (match_operand:<VEL> 4 "register_operand" " f, f, f, f"))] VCOPYSIGNS) - (match_operand:VF 2 "vector_merge_operand" " vu, 0, vu, 0")))] + (match_operand:V_VLSF 2 "vector_merge_operand" " vu, 0, vu, 0")))] "TARGET_VECTOR" "vfsgnj<nx>.vf\t%0,%3,%4%p1" [(set_attr "type" "vfsgnj") diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h index 2e07e908736..c7df879dbde 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/def.h @@ -175,6 +175,14 @@ typedef double v512df __attribute__ ((vector_size (4096))); a[i] = CALL (b[i], c[i]); \ } +#define DEF_CALL_VX(PREFIX, NUM, TYPE, CALL) \ + void __attribute__ ((noinline, noclone)) \ + PREFIX##_##TYPE##NUM (TYPE *restrict a, TYPE *restrict b, TYPE c) \ + { \ + for (int i = 0; i < NUM; ++i) \ + a[i] = CALL (b[i], c); \ + } + #define DEF_CONST(TYPE, VAL, NUM) \ void const_##TYPE##_##NUM (TYPE *restrict a) \ { \ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c new file mode 100644 index 00000000000..0cc18d91215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-1.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_CALL_VV (sgnj, 1, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 2, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 4, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 8, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 16, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 32, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 64, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 128, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 256, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 512, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 1024, _Float16, __builtin_copysignf16) +DEF_CALL_VV (sgnj, 2048, _Float16, __builtin_copysignf16) + +DEF_CALL_VV (sgnj, 1, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 2, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 4, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 8, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 16, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 32, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 64, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 128, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 256, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 512, float, __builtin_copysignf) +DEF_CALL_VV (sgnj, 1024, float, __builtin_copysignf) + +DEF_CALL_VV (sgnj, 1, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 2, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 4, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 8, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 16, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 32, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 64, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 128, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 256, double, __builtin_copysign) +DEF_CALL_VV (sgnj, 512, double, __builtin_copysign) + +/* { dg-final { scan-assembler-times {vfsgnj\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c new file mode 100644 index 00000000000..3a66481070a --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/vls/floating-point-sgnj-2.c @@ -0,0 +1,43 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zvl4096b -mabi=lp64d -O3 -fno-schedule-insns -fno-schedule-insns2 --param=riscv-autovec-lmul=m8 -ffast-math" } */ + +#include "def.h" + +DEF_CALL_VX (sgnj, 1, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 2, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 4, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 8, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 16, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 32, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 64, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 128, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 256, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 512, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 1024, _Float16, __builtin_copysignf16) +DEF_CALL_VX (sgnj, 2048, _Float16, __builtin_copysignf16) + +DEF_CALL_VX (sgnj, 1, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 2, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 4, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 8, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 16, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 32, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 64, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 128, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 256, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 512, float, __builtin_copysignf) +DEF_CALL_VX (sgnj, 1024, float, __builtin_copysignf) + +DEF_CALL_VX (sgnj, 1, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 2, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 4, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 8, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 16, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 32, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 64, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 128, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 256, double, __builtin_copysign) +DEF_CALL_VX (sgnj, 512, double, __builtin_copysign) + +/* { dg-final { scan-assembler-times {vfsgnj\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 30 } } */ +/* { dg-final { scan-assembler-not {csrr} } } */ -- 2.34.1
