LGTM Edwin Lu <e...@rivosinc.com> 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to vector instructions that were added after or were > missed by the original patch > https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html > > gcc/ChangeLog: > > * config/riscv/autovec-opt.md: Update types > * config/riscv/autovec.md: likewise > > Signed-off-by: Edwin Lu <e...@rivosinc.com> > --- > gcc/config/riscv/autovec-opt.md | 42 ++++++++++++++++++++++----------- > gcc/config/riscv/autovec.md | 28 +++++++++++++++------- > 2 files changed, 47 insertions(+), 23 deletions(-) > > diff --git a/gcc/config/riscv/autovec-opt.md > b/gcc/config/riscv/autovec-opt.md > index 1ca5ce97193..6cc1a01629c 100644 > --- a/gcc/config/riscv/autovec-opt.md > +++ b/gcc/config/riscv/autovec-opt.md > @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs<mode>" > gen_int_mode (GET_MODE_NUNITS > (<MODE>mode), Pmode), > const0_rtx)); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine vlmax neg and UNSPEC_VCOPYSIGN > (define_insn_and_split "*copysign<mode>_neg" > @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign<mode>_neg" > riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (<MODE>mode), > riscv_vector::BINARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf2) and vcond_mask > (define_insn_and_split "*cond_<optab><v_double_trunc><mode>" > @@ -765,7 +767,8 @@ (define_insn_and_split > "*cond_<optab><v_double_trunc><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf4) and vcond_mask > (define_insn_and_split "*cond_<optab><v_quad_trunc><mode>" > @@ -784,7 +787,8 @@ (define_insn_and_split > "*cond_<optab><v_quad_trunc><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine sign_extend/zero_extend(vf8) and vcond_mask > (define_insn_and_split "*cond_<optab><v_oct_trunc><mode>" > @@ -803,7 +807,8 @@ (define_insn_and_split > "*cond_<optab><v_oct_trunc><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine trunc(vf2) + vcond_mask > (define_insn_and_split "*cond_trunc<mode><v_double_trunc>" > @@ -823,7 +828,8 @@ (define_insn_and_split > "*cond_trunc<mode><v_double_trunc>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask > (define_insn_and_split "*cond_extend<v_double_trunc><mode>" > @@ -842,7 +848,8 @@ (define_insn_and_split > "*cond_extend<v_double_trunc><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine FP trunc(vf2) + vcond_mask > (define_insn_and_split "*cond_trunc<mode><v_double_trunc>" > @@ -862,7 +869,8 @@ (define_insn_and_split > "*cond_trunc<mode><v_double_trunc>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(FP->INT) + vcond_mask > (define_insn_and_split "*cond_<optab><mode><vconvert>" > @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_<optab><mode><vconvert>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(INT->FP) + vcond_mask > (define_insn_and_split "*cond_<float_cvt><vconvert><mode>" > @@ -902,7 +911,8 @@ (define_insn_and_split > "*cond_<float_cvt><vconvert><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(FP->2xINT) + vcond_mask > (define_insn_and_split "*cond_<optab><vnconvert><mode>" > @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_<optab><vnconvert><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(INT->2xFP) + vcond_mask > (define_insn_and_split "*cond_<float_cvt><vnconvert><mode>" > @@ -942,7 +953,8 @@ (define_insn_and_split > "*cond_<float_cvt><vnconvert><mode>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(2xFP->INT) + vcond_mask > (define_insn_and_split "*cond_<optab><mode><vnconvert>" > @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_<optab><mode><vnconvert>" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; Combine convert(2xINT->FP) + vcond_mask > (define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2" > @@ -982,4 +995,5 @@ (define_insn_and_split > "*cond_<float_cvt><mode><vnconvert>2" > gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)}; > riscv_vector::expand_cond_len_unop (icode, ops); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md > index 0f9d1fe2c8e..047a66b238f 100644 > --- a/gcc/config/riscv/autovec.md > +++ b/gcc/config/riscv/autovec.md > @@ -558,6 +558,7 @@ (define_insn_and_split "@vcond_mask_<mode><vm>" > riscv_vector::MERGE_OP, operands); > DONE; > } > + [(set_attr "type" "vector")] > ) > > ;; > ------------------------------------------------------------------------- > @@ -645,7 +646,8 @@ (define_insn_and_split "<optab><v_quad_trunc><mode>2" > insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vext")]) > > (define_insn_and_split "<optab><v_oct_trunc><mode>2" > [(set (match_operand:VOEXTI 0 "register_operand") > @@ -659,7 +661,8 @@ (define_insn_and_split "<optab><v_oct_trunc><mode>2" > insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vext")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [INT] Truncation > @@ -815,7 +818,8 @@ (define_insn_and_split "<optab><mode><vconvert>2" > insn_code icode = code_for_pred (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vfcvtftoi")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [FP<-INT] Conversions > @@ -837,7 +841,8 @@ (define_insn_and_split "<float_cvt><vconvert><mode>2" > insn_code icode = code_for_pred (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, > operands); > DONE; > -}) > +} > +[(set_attr "type" "vfcvtitof")]) > > ;; > ========================================================================= > ;; == Widening/narrowing Conversions > @@ -862,7 +867,8 @@ (define_insn_and_split "<optab><vnconvert><mode>2" > insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vfwcvtftoi")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [FP<-INT] Widening Conversions > @@ -883,7 +889,8 @@ (define_insn_and_split "<float_cvt><vnconvert><mode>2" > insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vfwcvtitof")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [INT<-FP] Narrowing Conversions > @@ -904,7 +911,8 @@ (define_insn_and_split "<optab><mode><vnconvert>2" > insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vfncvtftoi")]) > > ;; > ------------------------------------------------------------------------- > ;; ---- [FP<-INT] Narrowing Conversions > @@ -925,7 +933,8 @@ (define_insn_and_split "<float_cvt><mode><vnconvert>2" > insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, > operands); > DONE; > -}) > +} > +[(set_attr "type" "vfncvtitof")]) > > ;; > ========================================================================= > ;; == Unary arithmetic > @@ -986,7 +995,8 @@ (define_insn_and_split "<optab><mode>2" > insn_code icode = code_for_pred (<CODE>, <MODE>mode); > riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands); > DONE; > -}) > +} > +[(set_attr "type" "vector")]) > > ;; > ------------------------------------------------------------------------------- > ;; - [FP] Square root > -- > 2.34.1 > >
