This patch removes the incorrect earliest poset vsetvl optimization,
such bug was found in vect-double-reduc-5.c which is runtime(execution fail)
and also in PR111313.
For VLMAX intrinsics, we always emit a bogus patter which is vlmax_avl (see
vector.md) to
occupy a scalar register which is used by the following RVV instruction which
is VLMAX AVL.
Then for O2, O3, Ofast, earliest LCM works so well.
However, for O1, the vlmax_avl is not well optimized in the before pass which
confused LCM earliest
so that we will end up with some redundant vsetvli zero,zero instructions in
O1. (Note that O2 O3 Ofast are all good).
To elide those redundant vsetvli zero,zero, I added cleanup_earliest_vsetvls to
elide those redundant vsetvls.
Now, after I review the implementation of this post optimizaiton again, I found
it is incorrect and it is hard to
do the post optimizations for vsetvls that earliest LCM failed to eliminate.
Besides, such performance issues only happen in O1 or O0, such issues may not
be serious.
So remove it and we may will find another way (E.g. adjust vlmax_avl pattern
COST)
to optimize it if we really need to care about performance for O1.
PR target/111313
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::cleanup_earliest_vsetvls):
Remove.
(pass_vsetvl::df_post_optimization): Remove incorrect function.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-13.c: Adapt test.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c: Skip check for O1.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c: Ditto.
* gcc.target/riscv/rvv/autovec/pr111313.c: New test.
---
gcc/config/riscv/riscv-vsetvl.cc | 58 -------------------
.../gcc.target/riscv/rvv/autovec/pr111313.c | 20 +++++++
.../riscv/rvv/vsetvl/avl_single-13.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_bb_prop-17.c | 8 +--
.../riscv/rvv/vsetvl/vlmax_bb_prop-18.c | 8 +--
.../riscv/rvv/vsetvl/vlmax_bb_prop-19.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_bb_prop-20.c | 4 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-10.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-11.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-12.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-13.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-14.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-15.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-16.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-17.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-18.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-19.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-20.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-21.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-22.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-23.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-24.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-25.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-26.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-27.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_phi-28.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c | 2 +-
.../gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c | 2 +-
.../riscv/rvv/vsetvl/vlmax_switch_vtype-2.c | 2 +-
36 files changed, 61 insertions(+), 99 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index dd9aeb32b56..ae362a3f6a8 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2846,7 +2846,6 @@ private:
void ssa_post_optimization (void) const;
/* Phase 6. */
- bool cleanup_earliest_vsetvls (const basic_block) const;
void df_post_optimization (void) const;
void init (void);
@@ -4183,61 +4182,6 @@ has_no_uses (basic_block cfg_bb, rtx_insn *rinsn, int
regno)
return true;
}
-/* For many reasons, we failed to elide the redundant vsetvls
- in Phase 3 and Phase 4.
-
- - VLMAX-AVL case: 'vlmax_avl<mode>' may locate at some unlucky
- point which make us set ANTLOC as false for LCM in 'O1'.
- We don't want to complicate phase 3 and phase 4 too much,
- so we do the post optimization for redundant VSETVLs here.
-*/
-bool
-pass_vsetvl::cleanup_earliest_vsetvls (const basic_block cfg_bb) const
-{
- bool is_earliest_p = false;
- if (cfg_bb->index >= (int) m_vector_manager->vector_block_infos.length ())
- is_earliest_p = true;
-
- rtx_insn *rinsn
- = get_first_vsetvl_before_rvv_insns (cfg_bb, VSETVL_VTYPE_CHANGE_ONLY);
- if (!rinsn)
- return is_earliest_p;
-
- sbitmap avail;
- if (is_earliest_p)
- {
- gcc_assert (single_succ_p (cfg_bb) && single_pred_p (cfg_bb));
- const bb_info *pred_bb = crtl->ssa->bb (single_pred (cfg_bb));
- gcc_assert (pred_bb->index ()
- < m_vector_manager->vector_block_infos.length ());
- avail = m_vector_manager->vector_avout[pred_bb->index ()];
- }
- else
- avail = m_vector_manager->vector_avin[cfg_bb->index];
-
- if (!bitmap_empty_p (avail))
- {
- unsigned int bb_index;
- sbitmap_iterator sbi;
- vector_insn_info strictest_info = vector_insn_info ();
- EXECUTE_IF_SET_IN_BITMAP (avail, 0, bb_index, sbi)
- {
- const auto *expr = m_vector_manager->vector_exprs[bb_index];
- if (strictest_info.uninit_p ()
- || !expr->compatible_p (
- static_cast<const vl_vtype_info &> (strictest_info)))
- strictest_info = *expr;
- }
- vector_insn_info info;
- info.parse_insn (rinsn);
- if (!strictest_info.same_vtype_p (info))
- return is_earliest_p;
- eliminate_insn (rinsn);
- }
-
- return is_earliest_p;
-}
-
/* This function does the following post optimization base on dataflow
analysis:
@@ -4257,8 +4201,6 @@ pass_vsetvl::df_post_optimization (void) const
rtx_insn *rinsn;
FOR_ALL_BB_FN (cfg_bb, cfun)
{
- if (cleanup_earliest_vsetvls (cfg_bb))
- continue;
FOR_BB_INSNS (cfg_bb, rinsn)
{
if (NONDEBUG_INSN_P (rinsn) && vsetvl_insn_p (rinsn))
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
new file mode 100644
index 00000000000..1da1b8ce6fb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr111313.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64d
--param=riscv-autovec-preference=scalable -O3" } */
+
+#define K 32
+short in[2*K][K];
+short coeff[K][K];
+void
+foo ()
+{
+ for (int j = 0; j < K; j++)
+ {
+ for (int i = 0; i < 2*K; i++)
+ in[i][j] = i+j;
+
+ for (int i = 0; i < K; i++)
+ coeff[i][j] = i + 2;
+ }
+}
+
+/* { dg-final { scan-assembler-times
{vsetvli\s+zero,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 3 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
index 6b0ff255298..984d5593160 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-13.c
@@ -5,7 +5,7 @@
void f (int8_t * restrict in, int8_t * restrict out, int n, int cond)
{
- size_t vl = 101;
+ size_t vl = 101 + cond;
for (size_t i = 0; i < n; i++)
{
vint8mf8_t v = __riscv_vle8_v_i8mf8 (in + i, vl);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
index b5b31fdb593..5b2b2e1e32a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-17.c
@@ -171,7 +171,7 @@ void f6 (int * restrict in, int * restrict out, int n, int
cond)
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
index d2ec69a76f8..618e81285a1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-18.c
@@ -171,7 +171,7 @@ void f6 (int * restrict in, int * restrict out, int n, int
cond)
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle8\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle16\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
2 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
index 9fdc8aee6a1..6bdb2e9d182 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-19.c
@@ -31,4 +31,4 @@ void f6 (int * restrict in, int * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vle32\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
index e4caff3f9d1..db4f9a1da86 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-20.c
@@ -199,5 +199,5 @@ void f7 (int * restrict in, int * restrict out, int n, int
cond)
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
6 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times
{add\ta[0-7],a[0-7],a[0-7]\s+\.L[0-9][0-9]\:\s+vlm\.v\s+(?:v[0-9]|v[1-2][0-9]|v3[0-1]),0\s*\([a-x0-9]+\)}
6 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
index 9dc7392556a..830dfb83e6d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-1.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,\.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
index e132c036e7d..898dd20b0cc 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-10.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
index 10eb69a676e..24a3f55d92b 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-11.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
index fb13306a13b..f311cbfc12a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-12.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
index bfa51c0188e..2e0fbc5a817 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-13.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
index 402ec1bbccd..7a0e12f0ff3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-14.c
@@ -214,4 +214,4 @@ void f7 (void * restrict in, void * restrict out, int n,
int cond)
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\([a-x0-9]+\)}
7 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vlm\.v\s+v[0-9]+,0\([a-x0-9]+\)}
7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
index 1389c162f36..f61260780f2 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-15.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
index 5e3dd664931..4dcbf7bd1df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-16.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
index 0de0549c19f..0e0b67c5c61 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-17.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
index e76f934b8fe..5a5b7d57607 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-18.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
index c544b9b9d14..9e1f9c757c0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-19.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
index 7caccee7226..5ac8e179e73 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-2.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
index 5a3c986ade1..5ac73a979eb 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-20.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
index 5ef9c607038..f79559c48cd 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-21.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s+\.L[0-9]+\:\s+vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
index 46621b04b9e..a423c5dff28 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-22.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
index 50e484677f0..00d2f82c2d0 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-23.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
index 3d8bdbc1ef0..69f21e5cf95 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-24.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
index c4ffa48fccd..65709cd5f42 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-25.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
index ee4be66b360..4bf37250345 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-26.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
index d521e427b88..cacd290168e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-27.c
@@ -37,4 +37,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle32\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
index f215ac5ffba..39e747bd89a 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-28.c
@@ -234,4 +234,4 @@ void f7 (void * restrict in, void * restrict out, int n,
int cond)
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*v[0-9]+,0\([a-x0-9]+\)}
7 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vlm\.v\s*v[0-9]+,0\([a-x0-9]+\)}
7 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
index 3121f433840..dedadcb5351 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-3.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
index 1009517c609..31be96662a4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-4.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
index 7c8e5d3d859..5a48b997a71 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-5.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
index 35bb54eaef1..8ea534918ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-6.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle8\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
index 1d766651ce6..f4fa2696a1d 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-7.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
index 8c401140e82..8526ae610d3 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-8.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
index c6f9c0904cf..42180a70ab4 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_phi-9.c
@@ -34,4 +34,4 @@ void f (void * restrict in, void * restrict out, int n, int
cond)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 4 { target {
no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" no-opts "-flto" } } } } */
-/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
+/* { dg-final { scan-assembler-times
{ble\t[a-x0-9]+,zero,.L[0-9]+\s*\.L[0-9]+\:\s*vle16\.v\s+v[0-9]+,0\([a-x0-9]+\)}
1 { target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" no-opts "-flto" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
index 1702885796a..9d40a13b06e 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-2.c
@@ -23,4 +23,4 @@ void f (void * restrict in, void * restrict out, int n)
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-flto"
no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts "-flto" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 1 { target { no-opts "-O0"
no-opts "-O1" no-opts "-funroll-loops" no-opts "-Os" no-opts "-Oz" no-opts
"-flto" no-opts "-g" } } } } */
--
2.36.3
