[PATCH] RISC-V: Replace rtx REG for zero REGS operations

[Juzhe-Zhong]

This patch fixes these following FAILs:
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O0  (internal compiler error: 
in gen_reg_rtx, at emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O0  (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O1  (internal compiler error: 
in gen_reg_rtx, at emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O1  (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2  (internal compiler error: 
in gen_reg_rtx, at emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2  (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fno-use-linker-plugin 
-flto-partition=none  (internal compiler error: in gen_reg_rtx, at 
emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fno-use-linker-plugin 
-flto-partition=none  (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fuse-linker-plugin 
-fno-fat-lto-objects  (internal compiler error: in gen_reg_rtx, at 
emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O2 -flto -fuse-linker-plugin 
-fno-fat-lto-objects  (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O3 -g  (internal compiler 
error: in gen_reg_rtx, at emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -O3 -g  (test for excess errors)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -Os  (internal compiler error: 
in gen_reg_rtx, at emit-rtl.cc:1176)
FAIL: gcc.target/riscv/zero-scratch-regs-3.c   -Os  (test for excess errors)

These FAILs because regno_reg_rtx[regno] is VLS mode in some regno which is not 
VLMAX AVL
gcc/ChangeLog:

        * config/riscv/riscv.cc (vector_zero_call_used_regs): Fix bug.

---
 gcc/config/riscv/riscv.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index a3d3389e7e2..c0c9c990a23 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -8998,7 +8998,7 @@ vector_zero_call_used_regs (HARD_REG_SET 
need_zeroed_hardregs)
     {
       if (TEST_HARD_REG_BIT (need_zeroed_hardregs, regno))
        {
-         rtx target = regno_reg_rtx[regno];
+         rtx target = gen_rtx_REG (RVVM1SImode, regno);
          machine_mode mode = GET_MODE (target);
 
          if (!emitted_vlmax_vsetvl)
-- 
2.36.3