Accoring to Kito's advice, using "MASK(name) Var(other_flag_name)"
to generate MASK and TARGET MACRO automatically.
This patch improve the MACRO generation of MASK_* and TARGET_*.
Due to the more and more riscv extensions are added, the default target_flag
is full.
Before this patch,if you want to add new MACRO,you should define the
MACRO in the riscv-opts.h manually.
After this patch, you just need two steps:
1.Define the new TargetVariable.
2.Define "MASK(name) Var(new_target_flag).
gcc/ChangeLog:
* config/riscv/riscv-opts.h (MASK_ZICSR):
(MASK_ZIFENCEI): Delete;
(MASK_ZIHINTNTL): Ditto;
(MASK_ZIHINTPAUSE): Ditto;
(TARGET_ZICSR): Ditto;
(TARGET_ZIFENCEI): Ditto;
(TARGET_ZIHINTNTL): Ditto;
(TARGET_ZIHINTPAUSE):Ditto;
(MASK_ZAWRS): Ditto;
(TARGET_ZAWRS): Ditto;
(MASK_ZBA): Ditto;
(MASK_ZBB): Ditto;
(MASK_ZBC): Ditto;
(MASK_ZBS): Ditto;
(TARGET_ZBA): Ditto;
(TARGET_ZBB): Ditto;
(TARGET_ZBC): Ditto;
(TARGET_ZBS): Ditto;
(MASK_ZFINX): Ditto;
(MASK_ZDINX): Ditto;
(MASK_ZHINX): Ditto;
(MASK_ZHINXMIN): Ditto;
(TARGET_ZFINX): Ditto;
(TARGET_ZDINX): Ditto;
(TARGET_ZHINX): Ditto;
(TARGET_ZHINXMIN): Ditto;
(MASK_ZBKB): Ditto;
(MASK_ZBKC): Ditto;
(MASK_ZBKX): Ditto;
(MASK_ZKNE): Ditto;
(MASK_ZKND): Ditto;
(MASK_ZKNH): Ditto;
(MASK_ZKR): Ditto;
(MASK_ZKSED): Ditto;
(MASK_ZKSH): Ditto;
(MASK_ZKT): Ditto;
(TARGET_ZBKB): Ditto;
(TARGET_ZBKC): Ditto;
(TARGET_ZBKX): Ditto;
(TARGET_ZKNE): Ditto;
(TARGET_ZKND): Ditto;
(TARGET_ZKNH): Ditto;
(TARGET_ZKR): Ditto;
(TARGET_ZKSED): Ditto;
(TARGET_ZKSH): Ditto;
(TARGET_ZKT): Ditto;
(MASK_ZTSO): Ditto;
(TARGET_ZTSO): Ditto;
(MASK_VECTOR_ELEN_32): Ditto;
(MASK_VECTOR_ELEN_64): Ditto;
(MASK_VECTOR_ELEN_FP_32):Ditto;
(MASK_VECTOR_ELEN_FP_64):Ditto;
(MASK_VECTOR_ELEN_FP_16):Ditto;
(TARGET_VECTOR_ELEN_32): Ditto;
(TARGET_VECTOR_ELEN_64): Ditto;
(TARGET_VECTOR_ELEN_FP_32):Ditto;
(TARGET_VECTOR_ELEN_FP_64):Ditto;
(TARGET_VECTOR_ELEN_FP_16):Ditto;
(MASK_ZVBB): Ditto;
(MASK_ZVBC): Ditto;
(TARGET_ZVBB): Ditto;
(TARGET_ZVBC): Ditto;
(MASK_ZVKG): Ditto;
(MASK_ZVKNED): Ditto;
(MASK_ZVKNHA): Ditto;
(MASK_ZVKNHB): Ditto;
(MASK_ZVKSED): Ditto;
(MASK_ZVKSH): Ditto;
(MASK_ZVKN): Ditto;
(MASK_ZVKNC): Ditto;
(MASK_ZVKNG): Ditto;
(MASK_ZVKS): Ditto;
(MASK_ZVKSC): Ditto;
(MASK_ZVKSG): Ditto;
(MASK_ZVKT): Ditto;
(TARGET_ZVKG): Ditto;
(TARGET_ZVKNED): Ditto;
(TARGET_ZVKNHA): Ditto;
(TARGET_ZVKNHB): Ditto;
(TARGET_ZVKSED): Ditto;
(TARGET_ZVKSH): Ditto;
(TARGET_ZVKN): Ditto;
(TARGET_ZVKNC): Ditto;
(TARGET_ZVKNG): Ditto;
(TARGET_ZVKS): Ditto;
(TARGET_ZVKSC): Ditto;
(TARGET_ZVKSG): Ditto;
(TARGET_ZVKT): Ditto;
(MASK_ZVL32B): Ditto;
(MASK_ZVL64B): Ditto;
(MASK_ZVL128B): Ditto;
(MASK_ZVL256B): Ditto;
(MASK_ZVL512B): Ditto;
(MASK_ZVL1024B): Ditto;
(MASK_ZVL2048B): Ditto;
(MASK_ZVL4096B): Ditto;
(MASK_ZVL8192B): Ditto;
(MASK_ZVL16384B): Ditto;
(MASK_ZVL32768B): Ditto;
(MASK_ZVL65536B): Ditto;
(TARGET_ZVL32B): Ditto;
(TARGET_ZVL64B): Ditto;
(TARGET_ZVL128B): Ditto;
(TARGET_ZVL256B): Ditto;
(TARGET_ZVL512B): Ditto;
(TARGET_ZVL1024B): Ditto;
(TARGET_ZVL2048B): Ditto;
(TARGET_ZVL4096B): Ditto;
(TARGET_ZVL8192B): Ditto;
(TARGET_ZVL16384B): Ditto;
(TARGET_ZVL32768B): Ditto;
(TARGET_ZVL65536B): Ditto;
(MASK_ZICBOZ): Ditto;
(MASK_ZICBOM): Ditto;
(MASK_ZICBOP): Ditto;
(TARGET_ZICBOZ): Ditto;
(TARGET_ZICBOM): Ditto;
(TARGET_ZICBOP): Ditto;
(MASK_ZICOND): Ditto;
(TARGET_ZICOND): Ditto;
(MASK_ZFA): Ditto;
(TARGET_ZFA): Ditto;
(MASK_ZFHMIN): Ditto;
(MASK_ZFH): Ditto;
(MASK_ZVFHMIN): Ditto;
(MASK_ZVFH): Ditto;
(TARGET_ZFHMIN): Ditto;
(TARGET_ZFH): Ditto;
(TARGET_ZVFHMIN): Ditto;
(TARGET_ZVFH): Ditto;
(MASK_ZMMUL): Ditto;
(TARGET_ZMMUL): Ditto;
(MASK_ZCA): Ditto;
(MASK_ZCB): Ditto;
(MASK_ZCE): Ditto;
(MASK_ZCF): Ditto;
(MASK_ZCD): Ditto;
(MASK_ZCMP): Ditto;
(MASK_ZCMT): Ditto;
(TARGET_ZCA): Ditto;
(TARGET_ZCB): Ditto;
(TARGET_ZCE): Ditto;
(TARGET_ZCF): Ditto;
(TARGET_ZCD): Ditto;
(TARGET_ZCMP): Ditto;
(TARGET_ZCMT): Ditto;
(MASK_SVINVAL): Ditto;
(MASK_SVNAPOT): Ditto;
(TARGET_SVINVAL): Ditto;
(TARGET_SVNAPOT): Ditto;
(MASK_XTHEADBA): Ditto;
(MASK_XTHEADBB): Ditto;
(MASK_XTHEADBS): Ditto;
(MASK_XTHEADCMO): Ditto;
(MASK_XTHEADCONDMOV): Ditto;
(MASK_XTHEADFMEMIDX): Ditto;
(MASK_XTHEADFMV): Ditto;
(MASK_XTHEADINT): Ditto;
(MASK_XTHEADMAC): Ditto;
(MASK_XTHEADMEMIDX): Ditto;
(MASK_XTHEADMEMPAIR): Ditto;
(MASK_XTHEADSYNC): Ditto;
(TARGET_XTHEADBA): Ditto;
(TARGET_XTHEADBB): Ditto;
(TARGET_XTHEADBS): Ditto;
(TARGET_XTHEADCMO): Ditto;
(TARGET_XTHEADCONDMOV):Ditto;
(TARGET_XTHEADFMEMIDX):Ditto;
(TARGET_XTHEADFMV): Ditto;
(TARGET_XTHEADINT): Ditto;
(TARGET_XTHEADMAC): Ditto;
(TARGET_XTHEADMEMIDX): Ditto;
(TARGET_XTHEADMEMPAIR):Ditto;
(TARGET_XTHEADSYNC): Ditto;
(MASK_XVENTANACONDOPS):Ditto;
(TARGET_XVENTANACONDOPS):Ditto;
* config/riscv/riscv.opt: Add new Mask defination.
* opt-functions.awk: Add new function to find the index
of target variable from extra_target_vars.
* opt-read.awk: Add new function to store the Mask flags.
* opth-gen.awk: Add new function to output the defination of
Mask Macro and Target Macro.
---
gcc/config/riscv/riscv-opts.h | 218 +---------------------------------
gcc/config/riscv/riscv.opt | 176 +++++++++++++++++++++++++++
gcc/opt-functions.awk | 11 ++
gcc/opt-read.awk | 17 ++-
gcc/opth-gen.awk | 22 ++++
5 files changed, 226 insertions(+), 218 deletions(-)
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index a525f679683..7e4b0cc6fe1 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -101,191 +101,7 @@ enum riscv_entity
MAX_RISCV_ENTITIES
};
-#define MASK_ZICSR (1 << 0)
-#define MASK_ZIFENCEI (1 << 1)
-#define MASK_ZIHINTNTL (1 << 2)
-#define MASK_ZIHINTPAUSE (1 << 3)
-
-#define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0)
-#define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
-#define TARGET_ZIHINTNTL ((riscv_zi_subext & MASK_ZIHINTNTL) != 0)
-#define TARGET_ZIHINTPAUSE ((riscv_zi_subext & MASK_ZIHINTPAUSE) != 0)
-
-#define MASK_ZAWRS (1 << 0)
-#define TARGET_ZAWRS ((riscv_za_subext & MASK_ZAWRS) != 0)
-
-#define MASK_ZBA (1 << 0)
-#define MASK_ZBB (1 << 1)
-#define MASK_ZBC (1 << 2)
-#define MASK_ZBS (1 << 3)
-
-#define TARGET_ZBA ((riscv_zb_subext & MASK_ZBA) != 0)
-#define TARGET_ZBB ((riscv_zb_subext & MASK_ZBB) != 0)
-#define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0)
-#define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0)
-
-#define MASK_ZFINX (1 << 0)
-#define MASK_ZDINX (1 << 1)
-#define MASK_ZHINX (1 << 2)
-#define MASK_ZHINXMIN (1 << 3)
-
-#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0)
-#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0)
-#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0)
-#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0)
-
-#define MASK_ZBKB (1 << 0)
-#define MASK_ZBKC (1 << 1)
-#define MASK_ZBKX (1 << 2)
-#define MASK_ZKNE (1 << 3)
-#define MASK_ZKND (1 << 4)
-#define MASK_ZKNH (1 << 5)
-#define MASK_ZKR (1 << 6)
-#define MASK_ZKSED (1 << 7)
-#define MASK_ZKSH (1 << 8)
-#define MASK_ZKT (1 << 9)
-
-#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0)
-#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0)
-#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0)
-#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0)
-#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0)
-#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0)
-#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0)
-#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0)
-#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0)
-#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0)
-
-#define MASK_ZTSO (1 << 0)
-
-#define TARGET_ZTSO ((riscv_ztso_subext & MASK_ZTSO) != 0)
-
-#define MASK_VECTOR_ELEN_32 (1 << 0)
-#define MASK_VECTOR_ELEN_64 (1 << 1)
-#define MASK_VECTOR_ELEN_FP_32 (1 << 2)
-#define MASK_VECTOR_ELEN_FP_64 (1 << 3)
-/* Align the bit index to riscv-vector-builtins.h. */
-#define MASK_VECTOR_ELEN_FP_16 (1 << 6)
-
-#define TARGET_VECTOR_ELEN_32 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_32) != 0)
-#define TARGET_VECTOR_ELEN_64 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_64) != 0)
-#define TARGET_VECTOR_ELEN_FP_32 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_32) != 0)
-#define TARGET_VECTOR_ELEN_FP_64 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_64) != 0)
-#define TARGET_VECTOR_ELEN_FP_16 \
- ((riscv_vector_elen_flags & MASK_VECTOR_ELEN_FP_16) != 0)
-
-#define MASK_ZVBB (1 << 0)
-#define MASK_ZVBC (1 << 1)
-
-#define TARGET_ZVBB ((riscv_zvb_subext & MASK_ZVBB) != 0)
-#define TARGET_ZVBC ((riscv_zvb_subext & MASK_ZVBC) != 0)
-
-#define MASK_ZVKG (1 << 0)
-#define MASK_ZVKNED (1 << 1)
-#define MASK_ZVKNHA (1 << 2)
-#define MASK_ZVKNHB (1 << 3)
-#define MASK_ZVKSED (1 << 4)
-#define MASK_ZVKSH (1 << 5)
-#define MASK_ZVKN (1 << 6)
-#define MASK_ZVKNC (1 << 7)
-#define MASK_ZVKNG (1 << 8)
-#define MASK_ZVKS (1 << 9)
-#define MASK_ZVKSC (1 << 10)
-#define MASK_ZVKSG (1 << 11)
-#define MASK_ZVKT (1 << 12)
-
-#define TARGET_ZVKG ((riscv_zvk_subext & MASK_ZVKG) != 0)
-#define TARGET_ZVKNED ((riscv_zvk_subext & MASK_ZVKNED) != 0)
-#define TARGET_ZVKNHA ((riscv_zvk_subext & MASK_ZVKNHA) != 0)
-#define TARGET_ZVKNHB ((riscv_zvk_subext & MASK_ZVKNHB) != 0)
-#define TARGET_ZVKSED ((riscv_zvk_subext & MASK_ZVKSED) != 0)
-#define TARGET_ZVKSH ((riscv_zvk_subext & MASK_ZVKSH) != 0)
-#define TARGET_ZVKN ((riscv_zvk_subext & MASK_ZVKN) != 0)
-#define TARGET_ZVKNC ((riscv_zvk_subext & MASK_ZVKNC) != 0)
-#define TARGET_ZVKNG ((riscv_zvk_subext & MASK_ZVKNG) != 0)
-#define TARGET_ZVKS ((riscv_zvk_subext & MASK_ZVKS) != 0)
-#define TARGET_ZVKSC ((riscv_zvk_subext & MASK_ZVKSC) != 0)
-#define TARGET_ZVKSG ((riscv_zvk_subext & MASK_ZVKSG) != 0)
-#define TARGET_ZVKT ((riscv_zvk_subext & MASK_ZVKT) != 0)
-
-#define MASK_ZVL32B (1 << 0)
-#define MASK_ZVL64B (1 << 1)
-#define MASK_ZVL128B (1 << 2)
-#define MASK_ZVL256B (1 << 3)
-#define MASK_ZVL512B (1 << 4)
-#define MASK_ZVL1024B (1 << 5)
-#define MASK_ZVL2048B (1 << 6)
-#define MASK_ZVL4096B (1 << 7)
-#define MASK_ZVL8192B (1 << 8)
-#define MASK_ZVL16384B (1 << 9)
-#define MASK_ZVL32768B (1 << 10)
-#define MASK_ZVL65536B (1 << 11)
-
-#define TARGET_ZVL32B ((riscv_zvl_flags & MASK_ZVL32B) != 0)
-#define TARGET_ZVL64B ((riscv_zvl_flags & MASK_ZVL64B) != 0)
-#define TARGET_ZVL128B ((riscv_zvl_flags & MASK_ZVL128B) != 0)
-#define TARGET_ZVL256B ((riscv_zvl_flags & MASK_ZVL256B) != 0)
-#define TARGET_ZVL512B ((riscv_zvl_flags & MASK_ZVL512B) != 0)
-#define TARGET_ZVL1024B ((riscv_zvl_flags & MASK_ZVL1024B) != 0)
-#define TARGET_ZVL2048B ((riscv_zvl_flags & MASK_ZVL2048B) != 0)
-#define TARGET_ZVL4096B ((riscv_zvl_flags & MASK_ZVL4096B) != 0)
-#define TARGET_ZVL8192B ((riscv_zvl_flags & MASK_ZVL8192B) != 0)
-#define TARGET_ZVL16384B ((riscv_zvl_flags & MASK_ZVL16384B) != 0)
-#define TARGET_ZVL32768B ((riscv_zvl_flags & MASK_ZVL32768B) != 0)
-#define TARGET_ZVL65536B ((riscv_zvl_flags & MASK_ZVL65536B) != 0)
-
-#define MASK_ZICBOZ (1 << 0)
-#define MASK_ZICBOM (1 << 1)
-#define MASK_ZICBOP (1 << 2)
-
-#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0)
-#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0)
-#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0)
-
-#define MASK_ZICOND (1 << 2)
-#define TARGET_ZICOND ((riscv_zi_subext & MASK_ZICOND) != 0)
-
-#define MASK_ZFA (1 << 0)
-#define TARGET_ZFA ((riscv_zfa_subext & MASK_ZFA) != 0)
-
-#define MASK_ZFHMIN (1 << 0)
-#define MASK_ZFH (1 << 1)
-#define MASK_ZVFHMIN (1 << 2)
-#define MASK_ZVFH (1 << 3)
-
-#define TARGET_ZFHMIN ((riscv_zf_subext & MASK_ZFHMIN) != 0)
-#define TARGET_ZFH ((riscv_zf_subext & MASK_ZFH) != 0)
-#define TARGET_ZVFHMIN ((riscv_zf_subext & MASK_ZVFHMIN) != 0)
-#define TARGET_ZVFH ((riscv_zf_subext & MASK_ZVFH) != 0)
-
-#define MASK_ZMMUL (1 << 0)
-#define TARGET_ZMMUL ((riscv_zm_subext & MASK_ZMMUL) != 0)
-
-#define MASK_ZCA (1 << 0)
-#define MASK_ZCB (1 << 1)
-#define MASK_ZCE (1 << 2)
-#define MASK_ZCF (1 << 3)
-#define MASK_ZCD (1 << 4)
-#define MASK_ZCMP (1 << 5)
-#define MASK_ZCMT (1 << 6)
-
-#define TARGET_ZCA ((riscv_zc_subext & MASK_ZCA) != 0)
-#define TARGET_ZCB ((riscv_zc_subext & MASK_ZCB) != 0)
-#define TARGET_ZCE ((riscv_zc_subext & MASK_ZCE) != 0)
-#define TARGET_ZCF ((riscv_zc_subext & MASK_ZCF) != 0)
-#define TARGET_ZCD ((riscv_zc_subext & MASK_ZCD) != 0)
-#define TARGET_ZCMP ((riscv_zc_subext & MASK_ZCMP) != 0)
-#define TARGET_ZCMT ((riscv_zc_subext & MASK_ZCMT) != 0)
-
-#define MASK_SVINVAL (1 << 0)
-#define MASK_SVNAPOT (1 << 1)
-
-#define TARGET_SVINVAL ((riscv_sv_subext & MASK_SVINVAL) != 0)
-#define TARGET_SVNAPOT ((riscv_sv_subext & MASK_SVNAPOT) != 0)
+#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS &&
TARGET_64BIT))
/* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
@@ -295,38 +111,6 @@ enum riscv_entity
? 0 \
: 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
-#define MASK_XTHEADBA (1 << 0)
-#define MASK_XTHEADBB (1 << 1)
-#define MASK_XTHEADBS (1 << 2)
-#define MASK_XTHEADCMO (1 << 3)
-#define MASK_XTHEADCONDMOV (1 << 4)
-#define MASK_XTHEADFMEMIDX (1 << 5)
-#define MASK_XTHEADFMV (1 << 6)
-#define MASK_XTHEADINT (1 << 7)
-#define MASK_XTHEADMAC (1 << 8)
-#define MASK_XTHEADMEMIDX (1 << 9)
-#define MASK_XTHEADMEMPAIR (1 << 10)
-#define MASK_XTHEADSYNC (1 << 11)
-
-#define TARGET_XTHEADBA ((riscv_xthead_subext & MASK_XTHEADBA) != 0)
-#define TARGET_XTHEADBB ((riscv_xthead_subext & MASK_XTHEADBB) != 0)
-#define TARGET_XTHEADBS ((riscv_xthead_subext & MASK_XTHEADBS) != 0)
-#define TARGET_XTHEADCMO ((riscv_xthead_subext & MASK_XTHEADCMO) != 0)
-#define TARGET_XTHEADCONDMOV ((riscv_xthead_subext & MASK_XTHEADCONDMOV) != 0)
-#define TARGET_XTHEADFMEMIDX ((riscv_xthead_subext & MASK_XTHEADFMEMIDX) != 0)
-#define TARGET_XTHEADFMV ((riscv_xthead_subext & MASK_XTHEADFMV) != 0)
-#define TARGET_XTHEADINT ((riscv_xthead_subext & MASK_XTHEADINT) != 0)
-#define TARGET_XTHEADMAC ((riscv_xthead_subext & MASK_XTHEADMAC) != 0)
-#define TARGET_XTHEADMEMIDX ((riscv_xthead_subext & MASK_XTHEADMEMIDX) != 0)
-#define TARGET_XTHEADMEMPAIR ((riscv_xthead_subext & MASK_XTHEADMEMPAIR) != 0)
-#define TARGET_XTHEADSYNC ((riscv_xthead_subext & MASK_XTHEADSYNC) != 0)
-
-#define MASK_XVENTANACONDOPS (1 << 0)
-
-#define TARGET_XVENTANACONDOPS ((riscv_xventana_subext & MASK_XVENTANACONDOPS)
!= 0)
-
-#define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS &&
TARGET_64BIT))
-
/* We only enable VLS modes for VLA vectorization since fixed length VLMAX mode
is the highest priority choice and should not conflict with VLS modes. */
#define TARGET_VECTOR_VLS
\
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 569e9af2e30..037499af359 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -209,57 +209,233 @@ long riscv_stack_protector_guard_offset = 0
TargetVariable
int riscv_zi_subext
+Mask(ZICSR) Var(riscv_zi_subext)
+
+Mask(ZIFENCEI) Var(riscv_zi_subext)
+
+Mask(ZIHINTNTL) Var(riscv_zi_subext)
+
+Mask(ZIHINTPAUSE) Var(riscv_zi_subext)
+
+Mask(ZICOND) Var(riscv_zi_subext)
+
TargetVariable
int riscv_za_subext
+Mask(ZAWRS) Var(riscv_za_subext)
+
TargetVariable
int riscv_zb_subext
+Mask(ZBA) Var(riscv_zb_subext)
+
+Mask(ZBB) Var(riscv_zb_subext)
+
+Mask(ZBC) Var(riscv_zb_subext)
+
+Mask(ZBS) Var(riscv_zb_subext)
+
TargetVariable
int riscv_zinx_subext
+Mask(ZFINX) Var(riscv_zinx_subext)
+
+Mask(ZDINX) Var(riscv_zinx_subext)
+
+Mask(ZHINX) Var(riscv_zinx_subext)
+
+Mask(ZHINXMIN) Var(riscv_zinx_subext)
+
TargetVariable
int riscv_zk_subext
+Mask(ZBKB) Var(riscv_zk_subext)
+
+Mask(ZBKC) Var(riscv_zk_subext)
+
+Mask(ZBKX) Var(riscv_zk_subext)
+
+Mask(ZKNE) Var(riscv_zk_subext)
+
+Mask(ZKND) Var(riscv_zk_subext)
+
+Mask(ZKNH) Var(riscv_zk_subext)
+
+Mask(ZKR) Var(riscv_zk_subext)
+
+Mask(ZKSED) Var(riscv_zk_subext)
+
+Mask(ZKSH) Var(riscv_zk_subext)
+
+Mask(ZKT) Var(riscv_zk_subext)
+
TargetVariable
int riscv_vector_elen_flags
+Mask(VECTOR_ELEN_32) Var(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_64) Var(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_32) Var(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_64) Var(riscv_vector_elen_flags)
+
+Mask(VECTOR_ELEN_FP_16) Var(riscv_vector_elen_flags)
+
TargetVariable
int riscv_zvl_flags
+Mask(ZVL32B) Var(riscv_zvl_flags)
+
+Mask(ZVL64B) Var(riscv_zvl_flags)
+
+Mask(ZVL128B) Var(riscv_zvl_flags)
+
+Mask(ZVL256B) Var(riscv_zvl_flags)
+
+Mask(ZVL512B) Var(riscv_zvl_flags)
+
+Mask(ZVL1024B) Var(riscv_zvl_flags)
+
+Mask(ZVL2048B) Var(riscv_zvl_flags)
+
+Mask(ZVL4096B) Var(riscv_zvl_flags)
+
+Mask(ZVL8192B) Var(riscv_zvl_flags)
+
+Mask(ZVL16384B) Var(riscv_zvl_flags)
+
+Mask(ZVL32768B) Var(riscv_zvl_flags)
+
+Mask(ZVL65536B) Var(riscv_zvl_flags)
+
TargetVariable
int riscv_zvb_subext
+Mask(ZVBB) Var(riscv_zvb_subext)
+
+Mask(ZVBC) Var(riscv_zvb_subext)
+
TargetVariable
int riscv_zvk_subext
+Mask(ZVKG) Var(riscv_zvk_subext)
+
+Mask(ZVKNED) Var(riscv_zvk_subext)
+
+Mask(ZVKNHA) Var(riscv_zvk_subext)
+
+Mask(ZVKNHB) Var(riscv_zvk_subext)
+
+Mask(ZVKSED) Var(riscv_zvk_subext)
+
+Mask(ZVKSH) Var(riscv_zvk_subext)
+
+Mask(ZVKN) Var(riscv_zvk_subext)
+
+Mask(ZVKNC) Var(riscv_zvk_subext)
+
+Mask(ZVKNG) Var(riscv_zvk_subext)
+
+Mask(ZVKS) Var(riscv_zvk_subext)
+
+Mask(ZVKSC) Var(riscv_zvk_subext)
+
+Mask(ZVKSG) Var(riscv_zvk_subext)
+
+Mask(ZVKT) Var(riscv_zvk_subext)
+
TargetVariable
int riscv_zicmo_subext
+Mask(ZICBOZ) Var(riscv_zicmo_subext)
+
+Mask(ZICBOM) Var(riscv_zicmo_subext)
+
+Mask(ZICBOP) Var(riscv_zicmo_subext)
+
TargetVariable
int riscv_zf_subext
+Mask(ZFHMIN) Var(riscv_zf_subext)
+
+Mask(ZFH) Var(riscv_zf_subext)
+
+Mask(ZVFHMIN) Var(riscv_zf_subext)
+
+Mask(ZVFH) Var(riscv_zf_subext)
+
TargetVariable
int riscv_zfa_subext
+Mask(ZFA) Var(riscv_zfa_subext)
+
TargetVariable
int riscv_zm_subext
+Mask(ZMMUL) Var(riscv_zm_subext)
+
TargetVariable
int riscv_zc_subext
+Mask(ZCA) Var(riscv_zc_subext)
+
+Mask(ZCB) Var(riscv_zc_subext)
+
+Mask(ZCE) Var(riscv_zc_subext)
+
+Mask(ZCF) Var(riscv_zc_subext)
+
+Mask(ZCD) Var(riscv_zc_subext)
+
+Mask(ZCMP) Var(riscv_zc_subext)
+
+Mask(ZCMT) Var(riscv_zc_subext)
+
TargetVariable
int riscv_sv_subext
+Mask(SVINVAL) Var(riscv_sv_subext)
+
+Mask(SVNAPOT) Var(riscv_sv_subext)
+
TargetVariable
int riscv_ztso_subext
+Mask(ZTSO) Var(riscv_ztso_subext)
+
TargetVariable
int riscv_xthead_subext
+Mask(XTHEADBA) Var(riscv_xthead_subext)
+
+Mask(XTHEADBB) Var(riscv_xthead_subext)
+
+Mask(XTHEADBS) Var(riscv_xthead_subext)
+
+Mask(XTHEADCMO) Var(riscv_xthead_subext)
+
+Mask(XTHEADCONDMOV) Var(riscv_xthead_subext)
+
+Mask(XTHEADFMEMIDX) Var(riscv_xthead_subext)
+
+Mask(XTHEADFMV) Var(riscv_xthead_subext)
+
+Mask(XTHEADINT) Var(riscv_xthead_subext)
+
+Mask(XTHEADMAC) Var(riscv_xthead_subext)
+
+Mask(XTHEADMEMIDX) Var(riscv_xthead_subext)
+
+Mask(XTHEADMEMPAIR) Var(riscv_xthead_subext)
+
+Mask(XTHEADSYNC) Var(riscv_xthead_subext)
+
TargetVariable
int riscv_xventana_subext
+Mask(XVENTANACONDOPS) Var(riscv_xventana_subext)
+
Enum
Name(isa_spec_class) Type(enum riscv_isa_spec_class)
Supported ISA specs (for use with the -misa-spec= option):
diff --git a/gcc/opt-functions.awk b/gcc/opt-functions.awk
index 36de4639318..cbfcf7dabcf 100644
--- a/gcc/opt-functions.awk
+++ b/gcc/opt-functions.awk
@@ -387,3 +387,14 @@ function integer_range_info(range_option, init, option,
uinteger_used)
else
return "-1, -1"
}
+
+# Find the index of target variable from extra_target_vars
+function find_index(var, var_arry, n_var_arry)
+{
+ for (var_index = 0; var_index < n_var_arry; var_index++)
+ {
+ if (var_arry[var_index] == var)
+ break
+ }
+ return var_index
+}
diff --git a/gcc/opt-read.awk b/gcc/opt-read.awk
index fc4e3d77910..fcf92853957 100644
--- a/gcc/opt-read.awk
+++ b/gcc/opt-read.awk
@@ -22,6 +22,7 @@ BEGIN {
n_opts = 0
n_langs = 0
n_target_save = 0
+ n_target_vars = 0
n_extra_vars = 0
n_extra_target_vars = 0
n_extra_masks = 0
@@ -121,7 +122,21 @@ BEGIN {
n_opts++;
}
else {
- extra_masks[n_extra_masks++] = name
+ target_var = opt_args("Var", $0)
+ if (target_var)
+ {
+ target_var = opt_args("Var", $1)
+ var_index = find_index(target_var,
target_vars, n_target_vars)
+ if (var_index == n_target_vars)
+ {
+ target_vars[n_target_vars++] =
target_var
+ }
+
other_masks[var_index][n_other_mask[var_index]++] = name
+ }
+ else
+ {
+ extra_masks[n_extra_masks++] = name
+ }
}
}
}
diff --git a/gcc/opth-gen.awk b/gcc/opth-gen.awk
index 71404f9eff6..70ca3d37719 100644
--- a/gcc/opth-gen.awk
+++ b/gcc/opth-gen.awk
@@ -406,6 +406,18 @@ for (i = 0; i < n_extra_masks; i++) {
print "#define MASK_" extra_masks[i] " (1U << " masknum[""]++
")"
}
+for (i = 0; i < n_target_vars; i++)
+{
+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars)
== n_extra_target_vars)
+ continue
+ for (j = 0; j < n_other_mask[i]; j++)
+ {
+ print "#define MASK_" other_masks[i][j] " (1U << "
other_masknum[i][""]++ ")"
+ }
+ if (other_masknum[i][""] > 32)
+ print "#error too many target masks for" extra_target_vars[i]
+}
+
for (var in masknum) {
if (var != "" && host_wide_int[var] == "yes") {
print "#if defined(HOST_BITS_PER_WIDE_INT) && " masknum[var] "
> HOST_BITS_PER_WIDE_INT"
@@ -419,6 +431,16 @@ for (var in masknum) {
print "#error too many masks for " var
}
}
+for (i = 0; i < n_target_vars; i++)
+{
+ if (find_index(target_vars[i], extra_target_vars, n_extra_target_vars)
== n_extra_target_vars)
+ continue
+ for (j = 0; j < n_other_mask[i]; j++)
+ {
+ print "#define TARGET_" other_masks[i][j] \
+ " ((" target_vars[i] " & MASK_" other_masks[i][j] ") !=
0)"
+ }
+}
print ""
for (i = 0; i < n_opts; i++) {
--
2.17.1
