Hi Haochen,
on 2023/9/4 13:33, HAO CHEN GUI wrote:
> Hi,
> This patch implements 32bit inline lrint by "fctiw". It depends on
> the patch1 to do SImode move from FP registers on P7.
>
> Compared to last version, the main change is to add tests for "lrintf"
> and adjust the count of corresponding instructions.
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628436.html
>
> Bootstrapped and tested on powerpc64-linux BE and LE with no regressions.
>
> Thanks
> Gui Haochen
>
> ChangeLog
> rs6000: support 32bit inline lrint
>
> gcc/
> PR target/88558
> * config/rs6000/rs6000.md (lrint<mode>di2): Remove TARGET_FPRND
> from insn condition.
> (lrint<mode>si2): New insn pattern for 32bit lrint.
>
> gcc/testsuite/
> PR target/106769
> * gcc.target/powerpc/pr88558.h: New.
> * gcc.target/powerpc/pr88558-p7.c: New.
> * gcc.target/powerpc/pr88558-p8.c: New.
>
> patch.diff
> diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
> index edf49bd74e3..a41898e0e08 100644
> --- a/gcc/config/rs6000/rs6000.md
> +++ b/gcc/config/rs6000/rs6000.md
> @@ -6655,10 +6655,18 @@ (define_insn "lrint<mode>di2"
> [(set (match_operand:DI 0 "gpc_reg_operand" "=d")
> (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
> UNSPEC_FCTID))]
> - "TARGET_HARD_FLOAT && TARGET_FPRND"
> + "TARGET_HARD_FLOAT"
> "fctid %0,%1"
> [(set_attr "type" "fp")])
>
> +(define_insn "lrint<mode>si2"
> + [(set (match_operand:SI 0 "gpc_reg_operand" "=d")
> + (unspec:SI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")]
> + UNSPEC_FCTIW))]
> + "TARGET_HARD_FLOAT && TARGET_POPCNTD"
> + "fctiw %0,%1"
> + [(set_attr "type" "fp")])
> +
> (define_insn "btrunc<mode>2"
> [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,wa")
> (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "d,wa")]
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c
> b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c
> new file mode 100644
> index 00000000000..f302491c4d0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p7.c
> @@ -0,0 +1,13 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power7" } */
> +
> +/* -fno-math-errno is required to make {i,l,ll}rint inlined */
Nit: Comment is a bit out of date since now we have irintf.
> +
> +#include "pr88558.h"
> +
> +/* { dg-final { scan-assembler-times {\mfctid\M} 3 { target lp64 } } } */
> +/* { dg-final { scan-assembler-times {\mfctid\M} 1 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\mfctiw\M} 1 { target lp64 } } } */
> +/* { dg-final { scan-assembler-times {\mfctiw\M} 3 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\mstfiwx\M} 1 { target lp64 } } } */
> +/* { dg-final { scan-assembler-times {\mstfiwx\M} 3 { target ilp32 } } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c
> b/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c
> new file mode 100644
> index 00000000000..33398aa74c2
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr88558-p8.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target powerpc_p8vector_ok } */
> +/* { dg-options "-O2 -fno-math-errno -mdejagnu-cpu=power8" } */
> +
> +/* -fno-math-errno is required to make {i,l,ll}rint inlined */
Ditto.
> +
> +#include "pr88558.h"
> +
> +/* { dg-final { scan-assembler-times {\mfctid\M} 3 { target lp64 } } } */
> +/* { dg-final { scan-assembler-times {\mfctid\M} 1 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\mfctiw\M} 1 { target lp64 } } } */
> +/* { dg-final { scan-assembler-times {\mfctiw\M} 3 { target ilp32 } } } */
> +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 1 { target lp64 } } } */
> +/* { dg-final { scan-assembler-times {\mmfvsrwz\M} 3 { target ilp32 } } } */
> diff --git a/gcc/testsuite/gcc.target/powerpc/pr88558.h
> b/gcc/testsuite/gcc.target/powerpc/pr88558.h
> new file mode 100644
> index 00000000000..698640c0ef7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/pr88558.h
> @@ -0,0 +1,19 @@
> +long int test1 (double a)
> +{
> + return __builtin_lrint (a);
> +}
> +
> +long long test2 (double a)
> +{
> + return __builtin_llrint (a);
> +}
> +
> +int test3 (double a)
> +{
> + return __builtin_irint (a);
> +}
> +
> +long int test4 (float a)
> +{
> + return __builtin_lrintf (a);
> +}
As you added the extra coverage for irint and llrint excepting for lrint,
I'd expect you can also add the coverage for llrintf and irintf, to make
them consistent.
The others look good to me. Thanks!
BR,
Kewen
