gcc/
* config/xtensa/predicates.md (xtensa_cstoresi_operator): Add
unsigned comparisons.
* config/xtensa/xtensa.cc (xtensa_expand_scc): Add code
generation of salt/saltu instructions.
* config/xtensa/xtensa.h (TARGET_SALT): New macro.
* config/xtensa/xtensa.md (salt, saltu): New instruction
patterns.
---
gcc/config/xtensa/predicates.md | 2 +-
gcc/config/xtensa/xtensa.cc | 55 +++++++++++++++++++++++++++++++++
gcc/config/xtensa/xtensa.h | 1 +
gcc/config/xtensa/xtensa.md | 20 ++++++++++++
4 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/gcc/config/xtensa/predicates.md b/gcc/config/xtensa/predicates.md
index a3575a688923..672fb003a6c5 100644
--- a/gcc/config/xtensa/predicates.md
+++ b/gcc/config/xtensa/predicates.md
@@ -195,7 +195,7 @@
(match_code "plus,minus"))
(define_predicate "xtensa_cstoresi_operator"
- (match_code "eq,ne,gt,ge,lt,le"))
+ (match_code "eq,ne,gt,ge,lt,le,gtu,geu,ltu,leu"))
(define_predicate "xtensa_shift_per_byte_operator"
(match_code "ashift,ashiftrt,lshiftrt"))
diff --git a/gcc/config/xtensa/xtensa.cc b/gcc/config/xtensa/xtensa.cc
index 2481b028ca12..a4f8e3e49d06 100644
--- a/gcc/config/xtensa/xtensa.cc
+++ b/gcc/config/xtensa/xtensa.cc
@@ -995,6 +995,61 @@ xtensa_expand_scc (rtx operands[4], machine_mode cmp_mode)
rtx one_tmp, zero_tmp;
rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx);
+ if (cmp_mode == SImode && TARGET_SALT)
+ {
+ rtx a = operands[2], b = force_reg (SImode, operands[3]);
+ enum rtx_code code = GET_CODE (operands[1]);
+ bool invert_res = false;
+
+ switch (code)
+ {
+ case GE:
+ case GEU:
+ invert_res = true;
+ break;
+ case GT:
+ case GTU:
+ std::swap (a, b);
+ break;
+ case LE:
+ case LEU:
+ invert_res = true;
+ std::swap (a, b);
+ break;
+ default:
+ break;
+ }
+
+ switch (code)
+ {
+ case GE:
+ case GT:
+ case LE:
+ case LT:
+ emit_insn (gen_salt (dest, a, b));
+ if (!invert_res)
+ return 1;
+ break;
+ case GEU:
+ case GTU:
+ case LEU:
+ case LTU:
+ emit_insn (gen_saltu (dest, a, b));
+ if (!invert_res)
+ return 1;
+ break;
+ default:
+ break;
+ }
+
+ if (invert_res)
+ {
+ emit_insn (gen_negsi2 (dest, dest));
+ emit_insn (gen_addsi3 (dest, dest, const1_rtx));
+ return 1;
+ }
+ }
+
if (! (cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode,
operands[2], operands[3])))
return 0;
diff --git a/gcc/config/xtensa/xtensa.h b/gcc/config/xtensa/xtensa.h
index 34e06afcff48..5987681e5496 100644
--- a/gcc/config/xtensa/xtensa.h
+++ b/gcc/config/xtensa/xtensa.h
@@ -54,6 +54,7 @@ along with GCC; see the file COPYING3. If not see
#define TARGET_WINDOWED_ABI xtensa_windowed_abi
#define TARGET_DEBUG XCHAL_HAVE_DEBUG
#define TARGET_L32R XCHAL_HAVE_L32R
+#define TARGET_SALT (XTENSA_MARCH_EARLIEST >= 260000)
#define TARGET_DEFAULT (MASK_SERIALIZE_VOLATILE)
diff --git a/gcc/config/xtensa/xtensa.md b/gcc/config/xtensa/xtensa.md
index 6476fdc395ae..20af1cbfbd03 100644
--- a/gcc/config/xtensa/xtensa.md
+++ b/gcc/config/xtensa/xtensa.md
@@ -2393,6 +2393,26 @@
DONE;
})
+(define_insn "salt"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (lt:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))]
+ "TARGET_SALT"
+ "salt\t%0, %1, %2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "3")])
+
+(define_insn "saltu"
+ [(set (match_operand:SI 0 "register_operand" "=a")
+ (ltu:SI (match_operand:SI 1 "register_operand" "r")
+ (match_operand:SI 2 "register_operand" "r")))]
+ "TARGET_SALT"
+ "saltu\t%0, %1, %2"
+ [(set_attr "type" "arith")
+ (set_attr "mode" "SI")
+ (set_attr "length" "3")])
+
(define_expand "cstoresf4"
[(match_operand:SI 0 "register_operand")
(match_operator:SI 1 "comparison_operator"
--
2.30.2
