LGTM. You can commit it.
Thanks.
juzhe.zh...@rivai.ai
From: Patrick O'Neill
Date: 2023-09-20 02:04
To: gcc-patches
CC: juzhe.zhong; patrick; pan2.li; kito.cheng; yanzhang.wang; gnu-toolchain
Subject: [PATCH] RISC-V: Fix --enable-checking=rtl ICE on rv32gc bootstrap
Resolves PR 111461.
during RTL pass: expand
offtime.c: In function '__offtime':
offtime.c:79:6: internal compiler error: RTL check: expected elt 0 type 'e' or
'u', have 'w' (rtx const_int) in riscv_legitimize_const_move, at
config/riscv/riscv.cc:2176
79 | ip = __mon_yday[__isleap(y)];
Tested on rv32gc glibc with --enable-checking=rtl.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_const_move): Eliminate
src_op_0 var to avoid rtl check error.
Authored-by: Juzhe Zhong <juzhe.zh...@rivai.ai>
Tested-by: Patrick O'Neill <patr...@rivosinc.com>
---
gcc/config/riscv/riscv.cc | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 8c766e2e2be..9a1e643a6a8 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -2173,16 +2173,14 @@ riscv_legitimize_const_move (machine_mode mode, rtx
dest, rtx src)
(const_poly_int:DI [16, 16]) // <- op_1
))
*/
- rtx src_op_0 = XEXP (src, 0);
-
- if (GET_CODE (src) == CONST && GET_CODE (src_op_0) == PLUS
- && CONST_POLY_INT_P (XEXP (src_op_0, 1)))
+ if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS
+ && CONST_POLY_INT_P (XEXP (XEXP (src, 0), 1)))
{
rtx dest_tmp = gen_reg_rtx (mode);
rtx tmp = gen_reg_rtx (mode);
- riscv_emit_move (dest, XEXP (src_op_0, 0));
- riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (src_op_0, 1));
+ riscv_emit_move (dest, XEXP (XEXP (src, 0), 0));
+ riscv_legitimize_poly_move (mode, dest_tmp, tmp, XEXP (XEXP (src, 0),
1));
emit_insn (gen_rtx_SET (dest, gen_rtx_PLUS (mode, dest, dest_tmp)));
return;
--
2.34.1
