OK. But could you add a MACRO define Something like: #define MAX_POLY_VARIANT 64
juzhe.zh...@rivai.ai From: Kito Cheng Date: 2023-10-04 21:32 To: 钟居哲 CC: Jeff Law; gcc-patches; kito.cheng; palmer; rdapp Subject: Re: [PATCH] RISC-V: Fix the riscv_legitimize_poly_move issue on targets where the minimal VLEN exceeds 512. 钟居哲 <juzhe.zh...@rivai.ai>於 2023年10月4日 週三，20:20寫道： > > I think the "max poly value" is the LMUL 1 mode coeffs[1] > > See int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1]; > > So I think bump max_power to exact_log2 (64); is not enough. > since we adjust the LMUL 1 mode size according to TARGET_MIN_VLEN. > > I suspect the testcase you append in this patch will fail with > -march=rv64gcv_zvl4096b. There is no type smaller than [64, 64] in zvl4096b, RVVMF64BI is [64, 64], it’s smallest type, and RVVFM1BI is [512, 512] (size of single vector reg.) which at most 64x for zvl4096b, so my understanding is log2(64) is enough :) and of cause, verified the testcase is work with -march=rv64gcv_zvl4096b
