On Tue, Oct 10, 2023 at 5:08 AM Kito Cheng <kito.ch...@sifive.com> wrote:
>
> I guess you may also want to clean up those bodies for
> "check-function-bodies"?
I kept the comments on purpose, so that I have a basis for the
expected instruction counts.
But of course, there is no need to follow the format.
Would the following format change of the comments be ok?
-/*
-** ConEmv_imm_imm_reg:
-** addi a[0-9]+,a[0-9]+,-1000
-** li a[0-9]+,10
-** th\.mvnez a[0-9]+,a[0-9]+,a[0-9]+
-** ret
-*/
+/* addi aX, aX, -1000
+ li aX, 10
+ th.mvnez aX, aX, aX */
BR
Christoph
>
> On Mon, Oct 9, 2023 at 3:47 PM Christoph Muellner
> <christoph.muell...@vrull.eu> wrote:
> >
> > From: Christoph Müllner <christoph.muell...@vrull.eu>
> >
> > Fixes: c1bc7513b1d7 ("RISC-V: const: hide mvconst splitter from IRA")
> >
> > A recent change broke the xtheadcondmov-indirect tests, because the order of
> > emitted instructions changed. Since the test is too strict when testing for
> > a fixed instruction order, let's change the tests to simply count
> > instruction,
> > like it is done for similar tests.
> >
> > Reported-by: Patrick O'Neill <patr...@rivosinc.com>
> > Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> >
> > gcc/testsuite/ChangeLog:
> >
> > * gcc.target/riscv/xtheadcondmov-indirect.c: Make robust against
> > instruction reordering.
> >
> > Signed-off-by: Christoph Müllner <christoph.muell...@vrull.eu>
> > ---
> > .../gcc.target/riscv/xtheadcondmov-indirect.c | 11 ++++++++---
> > 1 file changed, 8 insertions(+), 3 deletions(-)
> >
> > diff --git a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> > b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> > index c3253ba5239..eba1b86137b 100644
> > --- a/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> > +++ b/gcc/testsuite/gcc.target/riscv/xtheadcondmov-indirect.c
> > @@ -1,8 +1,7 @@
> > /* { dg-do compile } */
> > -/* { dg-options "-march=rv32gc_xtheadcondmov -fno-sched-pressure" { target
> > { rv32 } } } */
> > -/* { dg-options "-march=rv64gc_xtheadcondmov -fno-sched-pressure" { target
> > { rv64 } } } */
> > +/* { dg-options "-march=rv32gc_xtheadcondmov" { target { rv32 } } } */
> > +/* { dg-options "-march=rv64gc_xtheadcondmov" { target { rv64 } } } */
> > /* { dg-skip-if "" { *-*-* } {"-O0" "-Os" "-Og" "-Oz" "-flto" } } */
> > -/* { dg-final { check-function-bodies "**" "" } } */
> >
> > /*
> > ** ConEmv_imm_imm_reg:
> > @@ -116,3 +115,9 @@ int ConNmv_reg_reg_reg(int x, int y, int z, int n)
> > return z;
> > return n;
> > }
> > +
> > +/* { dg-final { scan-assembler-times "addi\t" 5 } } */
> > +/* { dg-final { scan-assembler-times "li\t" 4 } } */
> > +/* { dg-final { scan-assembler-times "sub\t" 4 } } */
> > +/* { dg-final { scan-assembler-times "th.mveqz\t" 4 } } */
> > +/* { dg-final { scan-assembler-times "th.mvnez\t" 4 } } */
> > --
> > 2.41.0
> >
