Like ARM SVE and GCN, add RVV.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/bb-slp-pr69907.c: Add RVV.
---
gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
index b348526b62f..f63b42a271a 100644
--- a/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
+++ b/gcc/testsuite/gcc.dg/vect/bb-slp-pr69907.c
@@ -22,5 +22,5 @@ void foo(unsigned *p1, unsigned short *p2)
/* Disable for SVE because for long or variable-length vectors we don't
get an unrolled epilogue loop. Also disable for AArch64 Advanced SIMD,
because there we can vectorize the epilogue using mixed vector sizes.
- Likewise for AMD GCN. */
-/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a
load is not supported" "slp1" { target { { ! aarch64*-*-* } && { ! amdgcn*-*-*
} } } } } */
+ Likewise for AMD GCN and RVV. */
+/* { dg-final { scan-tree-dump "BB vectorization with gaps at the end of a
load is not supported" "slp1" { target { { ! aarch64*-*-* } && { { !
amdgcn*-*-* } && { ! riscv_v } } } } } } */
--
2.36.3
