From 98ada9501424404362a102eb356c77c32ff6e223 Mon Sep 17 00:00:00 2001 From: Kuan-Lin Chen Date: Sun, 18 Feb 2018 20:19:49 +0800 Subject: [PATCH] RISC-V: Support -mcmodel=large. --- gcc/config/riscv/predicates.md | 23 +++++-- gcc/config/riscv/riscv-c.cc | 4 ++ gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv-protos.h | 4 +- gcc/config/riscv/riscv.cc | 70 +++++++++++++++++++- gcc/config/riscv/riscv.h | 2 + gcc/config/riscv/riscv.md | 9 +++ gcc/config/riscv/riscv.opt | 3 + gcc/testsuite/gcc.target/riscv/large-model.c | 11 +++ 9 files changed, 120 insertions(+), 7 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/large-model.c diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 90567a817a7..f7ec66257c5 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -283,7 +283,8 @@ case SYMBOL_REF: case LABEL_REF: return riscv_symbolic_constant_p (op, &symbol_type) - && !riscv_split_symbol_type (symbol_type); + && !riscv_split_symbol_type (symbol_type) + && symbol_type != SYMBOL_FORCE_TO_MEM; case HIGH: op = XEXP (op, 0); @@ -320,9 +321,15 @@ }) (define_predicate "call_insn_operand" - (ior (match_operand 0 "absolute_symbolic_operand") - (match_operand 0 "plt_symbolic_operand") - (match_operand 0 "register_operand"))) + (match_operand 0 "general_operand") +{ + if (riscv_cmodel == CM_LARGE) + return register_operand (op, mode); + else + return (absolute_symbolic_operand (op, mode) + || plt_symbolic_operand (op, mode) + || register_operand (op, mode)); +}) (define_predicate "modular_operator" (match_code "plus,minus,mult,ashift")) @@ -605,3 +612,11 @@ (and (match_code "const_int") (ior (match_operand 0 "not_uimm_extra_bit_operand") (match_operand 0 "const_nottwobits_not_arith_operand")))) + +(define_predicate "pcrel_symbol_operand" + (match_code "symbol_ref") +{ + enum riscv_symbol_type type; + return (riscv_symbolic_constant_p (op, &type) + && type == SYMBOL_PCREL); +}) diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index bedf7217390..59f2062bf4d 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -101,6 +101,10 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) builtin_define ("__riscv_cmodel_medlow"); break; + case CM_LARGE: + builtin_define ("__riscv_cmodel_large"); + break; + case CM_PIC: case CM_MEDANY: builtin_define ("__riscv_cmodel_medany"); diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 532b1b6b84a..e30cca4d195 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -35,6 +35,7 @@ extern enum riscv_abi_type riscv_abi; enum riscv_code_model { CM_MEDLOW, CM_MEDANY, + CM_LARGE, CM_PIC }; extern enum riscv_code_model riscv_cmodel; diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 85d4f6ed9ea..7281405ed49 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -28,6 +28,7 @@ along with GCC; see the file COPYING3. If not see the unspec enum in riscv.md, subsequent to UNSPEC_ADDRESS_FIRST. */ enum riscv_symbol_type { SYMBOL_ABSOLUTE, + SYMBOL_FORCE_TO_MEM, SYMBOL_PCREL, SYMBOL_GOT_DISP, SYMBOL_TLS, @@ -158,7 +159,8 @@ extern bool riscv_shamt_matches_mask_p (int, HOST_WIDE_INT); extern void riscv_subword_address (rtx, rtx *, rtx *, rtx *, rtx *); extern void riscv_lshift_subword (machine_mode, rtx, rtx, rtx *); extern enum memmodel riscv_union_memmodels (enum memmodel, enum memmodel); - +extern void riscv_asm_output_pool_epilogue (FILE *, const char *, + tree, HOST_WIDE_INT); /* Routines implemented in riscv-c.cc. */ void riscv_cpu_cpp_builtins (cpp_reader *); void riscv_register_pragmas (void); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 08ff05dcc3f..68de813d875 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -287,6 +287,9 @@ bool riscv_user_wants_strict_align; /* Stack alignment to assume/maintain. */ unsigned riscv_stack_boundary; +/* Whether in riscv_output_mi_thunk. */ +static bool riscv_in_thunk_func = false; + /* If non-zero, this is an offset to be added to SP to redefine the CFA when restoring the FP register from the stack. Only valid when generating the epilogue. */ @@ -803,7 +806,17 @@ riscv_classify_symbol (const_rtx x) if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x)) return SYMBOL_GOT_DISP; - return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL; + switch (riscv_cmodel) + { + case CM_MEDLOW: + return SYMBOL_ABSOLUTE; + case CM_LARGE: + if (SYMBOL_REF_P (x)) + return CONSTANT_POOL_ADDRESS_P (x) ? SYMBOL_PCREL : SYMBOL_FORCE_TO_MEM; + return SYMBOL_PCREL; + default: + return SYMBOL_PCREL; + } } /* Classify the base of symbolic expression X. */ @@ -867,6 +880,7 @@ static int riscv_symbol_insns (enum riscv_symbol_type type) case SYMBOL_PCREL: return 2; /* AUIPC + the reference. */ case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference. */ case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference. */ + case SYMBOL_FORCE_TO_MEM: return 3; /* AUIPC + LD + the reference. */ default: gcc_unreachable (); } } @@ -1036,6 +1050,9 @@ riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) split_const (x, &base, &offset); if (riscv_symbolic_constant_p (base, &type)) { + if (type == SYMBOL_FORCE_TO_MEM) + return false; + /* As an optimization, don't spill symbolic constants that are as cheap to rematerialize as to access in the constant pool. */ if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0) @@ -1843,6 +1860,9 @@ riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out) if (low_out) switch (symbol_type) { + case SYMBOL_FORCE_TO_MEM: + return false; + case SYMBOL_ABSOLUTE: { rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); @@ -2000,7 +2020,20 @@ static rtx riscv_force_address (rtx x, machine_mode mode) { if (!riscv_legitimate_address_p (mode, x, false)) - x = force_reg (Pmode, x); + { + if (can_create_pseudo_p ()) + return force_reg (Pmode, x); + else + { + /* It's only safe for the thunk function. + Use ra as the temp regiater. */ + gcc_assert (riscv_in_thunk_func); + rtx reg = RISCV_PROLOGUE_TEMP2 (Pmode); + riscv_emit_move (reg, x); + return reg; + } + } + return x; } @@ -5702,12 +5735,24 @@ riscv_unique_section (tree decl, int reloc) default_unique_section (decl, reloc); } +/* Constant pools are per-function when in large code model. */ + +static inline bool +riscv_can_use_per_function_literal_pools_p (void) +{ + return riscv_cmodel == CM_LARGE; +} + /* Return a section for X, handling small data. */ static section * riscv_elf_select_rtx_section (machine_mode mode, rtx x, unsigned HOST_WIDE_INT align) { + /* The literal pool stays with the function. */ + if (riscv_can_use_per_function_literal_pools_p ()) + return function_section (current_function_decl); + section *s = default_elf_select_rtx_section (mode, x, align); if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode).to_constant ())) @@ -7927,6 +7972,8 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, rtx this_rtx, temp1, temp2, fnaddr; rtx_insn *insn; + riscv_in_thunk_func = true; + /* Pretend to be a post-reload pass while generating rtl. */ reload_completed = 1; @@ -7993,6 +8040,7 @@ riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, /* Clean up the vars set above. Note that final_end_function resets the global pointer for us. */ reload_completed = 0; + riscv_in_thunk_func = false; } /* Allocate a chunk of memory for per-function machine-dependent data. */ @@ -8133,6 +8181,18 @@ riscv_option_override (void) if (flag_pic) g_switch_value = 0; + /* Always prefer medlow than medany for RV32 since medlow can access + full address space. */ + if (riscv_cmodel == CM_LARGE && !TARGET_64BIT) + riscv_cmodel = CM_MEDLOW; + + if (riscv_cmodel == CM_LARGE && TARGET_EXPLICIT_RELOCS) + sorry ("code model %qs with %qs", "large", "-mexplicit-relocs"); + + if (riscv_cmodel == CM_LARGE && flag_pic) + sorry ("code model %qs with %qs", "large", + global_options.x_flag_pic > 1 ? "-fPIC" : "-fpic"); + if (flag_pic) riscv_cmodel = CM_PIC; @@ -8467,6 +8527,12 @@ riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, if (cfun->machine->interrupt_handler_p) return false; + /* Don't use sibcalls in the large model, because a sibcall instruction + expanding and a epilogue expanding both use RISCV_PROLOGUE_TEMP + register. */ + if (riscv_cmodel == CM_LARGE) + return false; + return true; } diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 1e9813b4f39..807fee06e0e 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -1200,4 +1200,6 @@ extern void riscv_remove_unneeded_save_restore_calls (void); #define HAVE_POST_MODIFY_DISP TARGET_XTHEADMEMIDX #define HAVE_PRE_MODIFY_DISP TARGET_XTHEADMEMIDX +#define ASM_OUTPUT_POOL_EPILOGUE riscv_asm_output_pool_epilogue + #endif /* ! GCC_RISCV_H */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ae2217d0907..f699f6d0f97 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -41,6 +41,7 @@ ;; Symbolic accesses. The order of this list must match that of ;; enum riscv_symbol_type in riscv-protos.h. UNSPEC_ADDRESS_FIRST + UNSPEC_FORCE_FOR_MEM UNSPEC_PCREL UNSPEC_LOAD_GOT UNSPEC_TLS @@ -3618,6 +3619,14 @@ FAIL; }) +(define_insn "*large_load_address" + [(set (match_operand:DI 0 "register_operand" "=r") + (mem:DI (match_operand 1 "pcrel_symbol_operand" "")))] + "TARGET_64BIT && riscv_cmodel == CM_LARGE" + "ld\t%0,%1" + [(set_attr "type" "load") + (set (attr "length") (const_int 8))]) + (include "bitmanip.md") (include "crypto.md") (include "sync.md") diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 70d78151cee..2a90a4836c1 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -123,6 +123,9 @@ Enum(code_model) String(medlow) Value(CM_MEDLOW) EnumValue Enum(code_model) String(medany) Value(CM_MEDANY) +EnumValue +Enum(code_model) String(large) Value(CM_LARGE) + mexplicit-relocs Target Mask(EXPLICIT_RELOCS) Use %reloc() operators, rather than assembly macros, to load addresses. diff --git a/gcc/testsuite/gcc.target/riscv/large-model.c b/gcc/testsuite/gcc.target/riscv/large-model.c new file mode 100644 index 00000000000..244d14e1878 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/large-model.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64 -fno-section-anchors -mcmodel=large" } */ +/* { dg-skip-if "" { *-*-* } {"-O0"} } */ +int a, b; +int foo1() +{ + return a*b; +} + +/* { dg-final { scan-assembler-times "ld.*LC0" 1 } } */ +/* { dg-final { scan-assembler-times "ld.*LC1" 1 } } */ -- 2.30.1