Fix segment fault on tuple move:
bbl loader
z 0000000000000000 ra 00000000000102ac sp 0000003ffffffaf0 gp 000000000001c0b8
tp 0000000000000000 t0 00000000000104a0 t1 000000000000000f t2 0000000000000000
s0 0000000000000000 s1 0000000000000000 a0 0000003ffffffb30 a1 0000003ffffffb58
a2 0000000000000000 a3 0000000000000000 a4 0000000000000000 a5 000000000001c340
a6 0000000000000004 a7 0000000000000004 s2 0000000000000000 s3 0000000000000000
s4 0000000000000000 s5 0000000000000000 s6 0000000000000000 s7 0000000000000000
s8 0000000000000000 s9 0000000000000000 sA 0000000000000000 sB 0000000000000000
t3 0000000000000000 t4 0000000000000000 t5 0000000000000000 t6 0000000000000000
pc 00000000000101aa va/inst 0000000000000004 sr 8000000200006620
User store segfault @ 0x0000000000000004
PR target/112561
gcc/ChangeLog:
* config/riscv/riscv-v.cc (emit_vlmax_insn_lra): Add VLS optimization.
(expand_tuple_move): Fix bug
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112561.c: New test.
---
gcc/config/riscv/riscv-v.cc | 21 ++++++++++++++++---
.../gcc.target/riscv/rvv/autovec/pr112561.c | 16 ++++++++++++++
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc
index 6a2009ffb05..08bbb657a06 100644
--- a/gcc/config/riscv/riscv-v.cc
+++ b/gcc/config/riscv/riscv-v.cc
@@ -374,10 +374,24 @@ void
emit_vlmax_insn_lra (unsigned icode, unsigned insn_flags, rtx *ops, rtx vl)
{
gcc_assert (!can_create_pseudo_p ());
+ machine_mode mode = GET_MODE (ops[0]);
- insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
- e.set_vl (vl);
- e.emit_insn ((enum insn_code) icode, ops);
+ if (imm_avl_p (mode))
+ {
+ /* Even though VL is a real hardreg already allocated since
+ it is post-RA now, we still gain benefits that we emit
+ vsetivli zero, imm instead of vsetvli VL, zero which is
+ we can be more flexible in post-RA instruction scheduling. */
+ insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, false);
+ e.set_vl (gen_int_mode (GET_MODE_NUNITS (mode), Pmode));
+ e.emit_insn ((enum insn_code) icode, ops);
+ }
+ else
+ {
+ insn_expander<RVV_INSN_OPERANDS_MAX> e (insn_flags, true);
+ e.set_vl (vl);
+ e.emit_insn ((enum insn_code) icode, ops);
+ }
}
/* Emit an RVV insn with a predefined vector length. Contrary to
@@ -2148,6 +2162,7 @@ expand_tuple_move (rtx *ops)
offset = ops[2];
}
+ emit_vlmax_vsetvl (subpart_mode, ops[4]);
if (MEM_P (ops[1]))
{
/* Load operations. */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
new file mode 100644
index 00000000000..25e61fa12c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112561.c
@@ -0,0 +1,16 @@
+/* { dg-do run { target { riscv_v } } } */
+/* { dg-options "-O3 -ftree-vectorize
--param=riscv-autovec-preference=fixed-vlmax -mcmodel=medlow" } */
+
+int printf(char *, ...);
+int a, b, c, e;
+short d[7][7] = {};
+int main() {
+ short f;
+ c = 0;
+ for (; c <= 6; c++) {
+ e |= d[c][c] & 1;
+ b &= f & 3;
+ }
+ printf("%d\n", a);
+ return 0;
+}
--
2.36.3
