>> I'm wondering whether the VLA modes in the iterator are correct. >> Looks dubious to me but unsure, will need to create some tests >> before continuing.
It must be correct. We already have test (intrinsic codes) for it. >> What's the problem with those? We probably won't reach there >> because the indexed is considered invalid before but we could, >> theoretically, still combine them? Condition should be put into iterators (Add a new iterator for indexed load store). Like you did on RAITO iterators adding !TARGET_64BIT. It's easier to maintain since iterators codes only happence once. Wheras this patch is adding GET_MODE_BITSIZE (GET_MODE_INNER (<VINDEX>mode)) <= GET_MODE_BITSIZE (Pmode) in many places. juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-17 22:55 To: 钟居哲; gcc-patches; palmer; kito.cheng; Jeff Law CC: rdapp.gcc Subject: Re: [PATCH] RISC-V: Disallow 64-bit indexed loads and stores for rv32gcv. > OK. Make sense。 I'm wondering whether the VLA modes in the iterator are correct. Looks dubious to me but unsure, will need to create some tests before continuing. > LGTM as long as you remove all > GET_MODE_BITSIZE (GET_MODE_INNER (<VINDEX>mode)) <= GET_MODE_BITSIZE (Pmode) What's the problem with those? We probably won't reach there because the indexed is considered invalid before but we could, theoretically, still combine them? Regards Robin
