This bug was discovered on PR112597, with -march=rv32gcv_zvl256b
--param=riscv-autovec-preference=fixed-vlmax
ICE:
bug.c:10:1: error: unrecognizable insn:
10 | }
| ^
(insn 10 9 11 2 (set (reg:V4SI 140)
(unspec:V4SI [
(unspec:V4BI [
(const_vector:V4BI [
(const_int 1 [0x1]) repeated x4
])
(const_int 4 [0x4])
(const_int 2 [0x2]) repeated x3
(reg:SI 66 vl)
(reg:SI 67 vtype)
] UNSPEC_VPREDICATE)
(unspec:V4SI [
(reg:SI 0 zero)
] UNSPEC_VUNDEF)
(subreg:V4SI (reg:V2DI 138 [ v ]) 0)
(subreg:SI (reg/v:DI 136 [ b ]) 0)
] UNSPEC_VSLIDE1DOWN)) "bug.c":8:10 -1
(nil))
The rootcase is we don't enable V4SImode, instead, we already have RVVMF2SI
which is totally same as V4SI
on -march=rv32gcv_zvl256 + --param=riscv-autovec-preference=fixed-vlmax.
The attribute VDEMODE map to V4SI is incorrect, we remove attributes and use
get_vector_mode to get
right mode.
PR target/112597
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Remove VDEMOTE and VMDEMOTE.
* config/riscv/vector.md: Fix slide1 intermediate mode bug.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/autovec/pr112597-1.c: New test.
---
gcc/config/riscv/vector-iterators.md | 28 -------------------
gcc/config/riscv/vector.md | 5 +++-
.../gcc.target/riscv/rvv/autovec/pr112597-1.c | 13 +++++++++
3 files changed, 17 insertions(+), 29 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
diff --git a/gcc/config/riscv/vector-iterators.md
b/gcc/config/riscv/vector-iterators.md
index 859f7bd1cdc..8c047e4c5e2 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -3198,34 +3198,6 @@
(V512DF "riscv_vector::vls_mode_valid_p (V512DFmode) &&
TARGET_VECTOR_ELEN_FP_64 && TARGET_MIN_VLEN >= 4096")
])
-(define_mode_attr VDEMOTE [
- (RVVM8DI "RVVM8SI") (RVVM4DI "RVVM4SI") (RVVM2DI "RVVM2SI") (RVVM1DI
"RVVM1SI")
- (V1DI "V2SI")
- (V2DI "V4SI")
- (V4DI "V8SI")
- (V8DI "V16SI")
- (V16DI "V32SI")
- (V32DI "V64SI")
- (V64DI "V128SI")
- (V128DI "V256SI")
- (V256DI "V512SI")
- (V512DI "V1024SI")
-])
-
-(define_mode_attr VMDEMOTE [
- (RVVM8DI "RVVMF4BI") (RVVM4DI "RVVMF8BI") (RVVM2DI "RVVMF16BI") (RVVM1DI
"RVVMF32BI")
- (V1DI "V2BI")
- (V2DI "V4BI")
- (V4DI "V8BI")
- (V8DI "V16BI")
- (V16DI "V32BI")
- (V32DI "V64BI")
- (V64DI "V128BI")
- (V128DI "V256BI")
- (V256DI "V512BI")
- (V512DI "V1024BI")
-])
-
(define_mode_attr stride_predicate [
(RVVM8QI "vector_eew8_stride_operand") (RVVM4QI "vector_eew8_stride_operand")
(RVVM2QI "vector_eew8_stride_operand") (RVVM1QI "vector_eew8_stride_operand")
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index d1499d330ff..4aed25e54f1 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -8096,8 +8096,11 @@
(match_operand:<VEL> 4 "reg_or_int_operand")] VSLIDES1))]
"TARGET_VECTOR"
{
+ poly_uint64 nunits = GET_MODE_NUNITS (<MODE>mode) * 2;
+ machine_mode vsimode = riscv_vector::get_vector_mode (SImode,
nunits).require ();
+ machine_mode vbimode = riscv_vector::get_vector_mode (BImode,
nunits).require ();
if (riscv_vector::slide1_sew64_helper (<UNSPEC>, <MODE>mode,
- <VDEMOTE>mode, <VMDEMOTE>mode,
+ vsimode, vbimode,
operands))
DONE;
})
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
new file mode 100644
index 00000000000..73aa3ee2f51
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112597-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv32gcv_zvl256b -mabi=ilp32d -O3 --param
riscv-autovec-preference=fixed-vlmax" } */
+
+#include <stdint-gcc.h>
+
+typedef int64_t vnx2di __attribute__ ((vector_size (16)));
+
+__attribute__ ((noipa)) void
+f_vnx2di (int64_t a, int64_t b, int64_t *out)
+{
+ vnx2di v = {a, b};
+ *(vnx2di *) out = v;
+}
--
2.36.3
