>> Looks like this already went in while I was looking at it... I committed it after kito approve that.
>> I can't really match spec and code. For the lmul = 2 case sure, >> but W84 e.g. allows v4 and not v6? What actually is "highest-numbered part"? Yes. For vwcvt, LMUL 4 -> LMUL 8. We allow overlap vwcvt v0 (occupy v0 - v7), v4 (occupy v4 - v7) This patch support the overlap above. Without this patch, vwcvt is completely non-overlap in any register. >>The name vconstraint doesn't say anything. This is kito's code. Could you suggest another name ? I can modify it. >>Regarding earlyclobber. We still don't consume all inputs before >>writing them (there is overlap after all). Is that the gist of >>the change? Circumventing the earlyclobber by "strategically" >>selecting registers? >>Why is the disparage necessary? What happens if it's not there? I experiment with many tests, turns out adding ? generate better codegen. You can try it (remove ?) and testing it on case (I added in this patch). juzhe.zh...@rivai.ai From: Robin Dapp Date: 2023-11-29 19:01 To: Juzhe-Zhong; gcc-patches CC: rdapp.gcc; kito.cheng; kito.cheng; jeffreyalaw Subject: Re: [PATCH] RISC-V: Support highpart register overlap for vwcvt Looks like this already went in while I was looking at it... In general it looks ok to me but I would have really hoped for some more comments. > +;; These following constraints are used by RVV instructions with dest EEW > > src EEW. > +;; RISC-V 'V' Spec 5.2. Vector Operands: > +;; The destination EEW is greater than the source EEW, the source EMUL is at > least 1, > +;; and the overlap is in the highest-numbered part of the destination > register group. > +;; (e.g., when LMUL=8, vzext.vf4 v0, v6 is legal, but a source of v0, v2, or > v4 is not). > +(define_register_constraint "W21" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register has register number % 2 == 1." "regno % 2 == 1") > + > +(define_register_constraint "W42" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register has register number % 4 == 2." "regno % 4 == 2") > + > +(define_register_constraint "W84" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register has register number % 8 == 4." "regno % 8 == 4") > + > +(define_register_constraint "W41" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register has register number % 4 == 1." "regno % 4 == 1") > + > +(define_register_constraint "W81" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register has register number % 8 == 1." "regno % 8 == 1") > + > +(define_register_constraint "W82" "TARGET_VECTOR ? V_REGS : NO_REGS" > + "A vector register has register number % 8 == 2." "regno % 8 == 2") > + I can't really match spec and code. For the lmul = 2 case sure, but W84 e.g. allows v4 and not v6? What actually is "highest-numbered part"? > +(define_attr "vconstraint" "no,W21,W42,W84,W41,W81,W82" > + (const_string "no")) > + > +(define_attr "vconstraint_enabled" "no,yes" > + (cond [(eq_attr "vconstraint" "no") > + (const_string "yes") > + > + (and (eq_attr "vconstraint" "W21") > + (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != > 2")) > + (const_string "no") > + > + (and (eq_attr "vconstraint" "W42,W41") > + (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != > 4")) > + (const_string "no") > + > + (and (eq_attr "vconstraint" "W84,W81,W82") > + (match_test "riscv_get_v_regno_alignment (GET_MODE (operands[0])) != > 8")) > + (const_string "no") > + ] > + (const_string "yes"))) > + The name vconstraint doesn't say anything. > ;; vwcvt<u>.x.x.v > (define_insn "@pred_<optab><mode>" > - [(set (match_operand:VWEXTI 0 "register_operand" > "=&vr,&vr") > + [(set (match_operand:VWEXTI 0 "register_operand" "=vr, > vr, vr, vr, vr, vr, ?&vr, ?&vr") Regarding earlyclobber. We still don't consume all inputs before writing them (there is overlap after all). Is that the gist of the change? Circumventing the earlyclobber by "strategically" selecting registers? Why is the disparage necessary? What happens if it's not there? Regards Robin
