From: Pan Li <pan2...@intel.com> This patch fixes the following FAIL: Running target riscv-sim/-march=rv64gcv/-mabi=lp64d/-mcmodel=medlow/--param=riscv-autovec-lmul=m8 FAIL: gcc.dg/vect/fast-math-vect-complex-3.c execution test
The root cause is we generate incorrect codegen for (const_poly_int:DI [549755813888, 549755813888]) Before this patch: li a7,0 vmv.v.x v0,a7 After this patch: csrr a2,vlenb slli a2,a2,33 vmv.v.x v0,a2 gcc/ChangeLog: * config/riscv/riscv.cc (riscv_expand_mult_with_const_int): Change int into HOST_WIDE_INT. (riscv_legitimize_poly_move): Ditto. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/bug-3.c: New test. Signed-off-by: Pan Li <pan2...@intel.com> --- gcc/config/riscv/riscv.cc | 10 +++-- .../gcc.target/riscv/rvv/autovec/bug-3.c | 39 +++++++++++++++++++ 2 files changed, 45 insertions(+), 4 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index f60726711e8..3fef1ab1514 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2371,7 +2371,7 @@ riscv_expand_op (enum rtx_code code, machine_mode mode, rtx op0, rtx op1, static void riscv_expand_mult_with_const_int (machine_mode mode, rtx dest, rtx multiplicand, - int multiplier) + HOST_WIDE_INT multiplier) { if (multiplier == 0) { @@ -2380,7 +2380,7 @@ riscv_expand_mult_with_const_int (machine_mode mode, rtx dest, rtx multiplicand, } bool neg_p = multiplier < 0; - int multiplier_abs = abs (multiplier); + unsigned HOST_WIDE_INT multiplier_abs = abs (multiplier); if (multiplier_abs == 1) { @@ -2475,8 +2475,10 @@ void riscv_legitimize_poly_move (machine_mode mode, rtx dest, rtx tmp, rtx src) { poly_int64 value = rtx_to_poly_int64 (src); - int offset = value.coeffs[0]; - int factor = value.coeffs[1]; + /* It use HOST_WIDE_INT intead of int since 32bit type is not enough + for e.g. (const_poly_int:DI [549755813888, 549755813888]). */ + HOST_WIDE_INT offset = value.coeffs[0]; + HOST_WIDE_INT factor = value.coeffs[1]; int vlenb = BYTES_PER_RISCV_VECTOR.coeffs[1]; int div_factor = 0; /* Calculate (const_poly_int:MODE [m, n]) using scalar instructions. diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c new file mode 100644 index 00000000000..643e91b918e --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/bug-3.c @@ -0,0 +1,39 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvl512b -mabi=lp64d --param=riscv-autovec-lmul=m8 --param=riscv-autovec-preference=scalable -fno-vect-cost-model -O2 -ffast-math" } */ + +#define N 16 + +_Complex float a[N] = + { 10.0F + 20.0iF, 11.0F + 21.0iF, 12.0F + 22.0iF, 13.0F + 23.0iF, + 14.0F + 24.0iF, 15.0F + 25.0iF, 16.0F + 26.0iF, 17.0F + 27.0iF, + 18.0F + 28.0iF, 19.0F + 29.0iF, 20.0F + 30.0iF, 21.0F + 31.0iF, + 22.0F + 32.0iF, 23.0F + 33.0iF, 24.0F + 34.0iF, 25.0F + 35.0iF }; +_Complex float b[N] = + { 30.0F + 40.0iF, 31.0F + 41.0iF, 32.0F + 42.0iF, 33.0F + 43.0iF, + 34.0F + 44.0iF, 35.0F + 45.0iF, 36.0F + 46.0iF, 37.0F + 47.0iF, + 38.0F + 48.0iF, 39.0F + 49.0iF, 40.0F + 50.0iF, 41.0F + 51.0iF, + 42.0F + 52.0iF, 43.0F + 53.0iF, 44.0F + 54.0iF, 45.0F + 55.0iF }; + +_Complex float c[N]; +_Complex float res[N] = + { -500.0F + 1000.0iF, -520.0F + 1102.0iF, + -540.0F + 1208.0iF, -560.0F + 1318.0iF, + -580.0F + 1432.0iF, -600.0F + 1550.0iF, + -620.0F + 1672.0iF, -640.0F + 1798.0iF, + -660.0F + 1928.0iF, -680.0F + 2062.0iF, + -700.0F + 2200.0iF, -720.0F + 2342.0iF, + -740.0F + 2488.0iF, -760.0F + 2638.0iF, + -780.0F + 2792.0iF, -800.0F + 2950.0iF }; + + +void +foo (void) +{ + int i; + + for (i = 0; i < N; i++) + c[i] = a[i] * b[i]; +} + +/* { dg-final { scan-assembler-not {li\s+[a-x0-9]+,\s*0} } } */ +/* { dg-final { scan-assembler-times {slli\s+[a-x0-9]+,\s*[a-x0-9]+,\s*33} 1 } } */ -- 2.34.1