[PATCH] testsuite: Fix cpymem-1.c dump checks under different riscv-sim for RVV.

[Li Xu]

From: xuli <xu...@eswincomputing.com>

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/rvv/base/cpymem-1.c: Fix checks.
---
 .../gcc.target/riscv/rvv/base/cpymem-1.c      | 27 +++++++++++++++++--
 1 file changed, 25 insertions(+), 2 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c 
b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
index 549d6648104..aac81079650 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/cpymem-1.c
@@ -50,11 +50,34 @@ void f2 (__INT32_TYPE__* a, __INT32_TYPE__* b, int l)
    Use extern here so that we get a known alignment, lest
    DATA_ALIGNMENT force us to make the scan pattern accomodate
    code for different alignments depending on word size.
-** f3: { target { any-opts "-mcmodel=medlow" } }
+** f3: { target { { any-opts "-mcmodel=medlow" } && { no-opts 
"-march=rv64gcv_zvl512b" "-march=rv64gcv_zvl1024b" 
"--param=riscv-autovec-lmul=dynamic" "--param=riscv-autovec-lmul=m2" 
"--param=riscv-autovec-lmul=m4" "--param=riscv-autovec-lmul=m8" 
"--param=riscv-autovec-preference=fixed-vlmax" } } }
 **        lui\s+[ta][0-7],%hi\(a_a\)
+**        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
 **        lui\s+[ta][0-7],%hi\(a_b\)
 **        addi\s+a4,[ta][0-7],%lo\(a_b\)
-**        vsetivli\s+zero,16,e32,m4,ta,ma
+**        vsetivli\s+zero,16,e32,m8,ta,ma
+**        vle32.v\s+v\d+,0\([ta][0-7]\)
+**        vse32\.v\s+v\d+,0\([ta][0-7]\)
+**        ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medlow 
--param=riscv-autovec-preference=fixed-vlmax" "-mcmodel=medlow 
-march=rv64gcv_zvl512b --param=riscv-autovec-preference=fixed-vlmax" } && { 
no-opts "-march=rv64gcv_zvl1024b" } } }
+**        lui\s+[ta][0-7],%hi\(a_a\)
+**        lui\s+[ta][0-7],%hi\(a_b\)
+**        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
+**        addi\s+a4,[ta][0-7],%lo\(a_b\)
+**        vl(1|4|2)re32\.v\s+v\d+,0\([ta][0-7]\)
+**        vs(1|4|2)r\.v\s+v\d+,0\([ta][0-7]\)
+**        ret
+*/
+
+/*
+** f3: { target { { any-opts "-mcmodel=medlow -march=rv64gcv_zvl1024b" 
"-mcmodel=medlow -march=rv64gcv_zvl512b" } && { no-opts 
"--param=riscv-autovec-preference=fixed-vlmax" } } }
+**        lui\s+[ta][0-7],%hi\(a_a\)
+**        lui\s+[ta][0-7],%hi\(a_b\)
+**        addi\s+a4,[ta][0-7],%lo\(a_b\)
+**        vsetivli\s+zero,16,e32,(m1|m4|mf2),ta,ma
 **        vle32.v\s+v\d+,0\([ta][0-7]\)
 **        addi\s+[ta][0-7],[ta][0-7],%lo\(a_a\)
 **        vse32\.v\s+v\d+,0\([ta][0-7]\)
-- 
2.17.1