This patch adds th. prefix to all XTheadVector instructions by implementing new assembly output functions. We only check the prefix is 'v', so that no extra attribute is needed.
gcc/ChangeLog: * config/riscv/riscv-protos.h (riscv_asm_output_opcode): Add new function to add assembler insn code prefix/suffix. (th_asm_output_opcode): Add Thead function to add assembler insn code prefix/suffix. * config/riscv/riscv.cc (riscv_asm_output_opcode): Implement function to add assembler insn code prefix/suffix. * config/riscv/riscv.h (ASM_OUTPUT_OPCODE): Add new function to add assembler insn code prefix/suffix. * config/riscv/thead.cc (th_asm_output_opcode): Implement Thead function to add assembler insn code prefix/suffix. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/xtheadvector/prefix.c: New test. Co-authored-by: Jin Ma <ji...@linux.alibaba.com> Co-authored-by: Xianmiao Qu <cooper...@linux.alibaba.com> Co-authored-by: Christoph Müllner <christoph.muell...@vrull.eu> --- gcc/config/riscv/riscv-protos.h | 2 ++ gcc/config/riscv/riscv.cc | 11 +++++++++++ gcc/config/riscv/riscv.h | 4 ++++ gcc/config/riscv/thead.cc | 13 +++++++++++++ .../gcc.target/riscv/rvv/xtheadvector/prefix.c | 12 ++++++++++++ 5 files changed, 42 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 31049ef7523..71724dabdb5 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -102,6 +102,7 @@ struct riscv_address_info { }; /* Routines implemented in riscv.cc. */ +extern const char *riscv_asm_output_opcode (FILE *asm_out_file, const char *p); extern enum riscv_symbol_type riscv_classify_symbolic_expression (rtx); extern bool riscv_symbolic_constant_p (rtx, enum riscv_symbol_type *); extern int riscv_float_const_rtx_index_for_fli (rtx); @@ -717,6 +718,7 @@ extern void th_mempair_prepare_save_restore_operands (rtx[4], bool, int, HOST_WIDE_INT, int, HOST_WIDE_INT); extern void th_mempair_save_restore_regs (rtx[4], bool, machine_mode); +extern const char *th_asm_output_opcode (FILE *asm_out_file, const char *p); #ifdef RTX_CODE extern const char* th_mempair_output_move (rtx[4], bool, machine_mode, RTX_CODE); diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 0d1cbc5cb5f..51878797287 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5636,6 +5636,17 @@ riscv_get_v_regno_alignment (machine_mode mode) return lmul; } +/* Define ASM_OUTPUT_OPCODE to do anything special before + emitting an opcode. */ +const char * +riscv_asm_output_opcode (FILE *asm_out_file, const char *p) +{ + if (TARGET_XTHEADVECTOR) + return th_asm_output_opcode (asm_out_file, p); + + return p; +} + /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 'h' Print the high-part relocation associated with OP, after stripping diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 6df9ec73c5e..c33361a254d 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -826,6 +826,10 @@ extern enum riscv_cc get_riscv_cc (const rtx use); asm_fprintf ((FILE), "%U%s", (NAME)); \ } while (0) +#undef ASM_OUTPUT_OPCODE +#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ + (PTR) = riscv_asm_output_opcode(STREAM, PTR) + #define JUMP_TABLES_IN_TEXT_SECTION 0 #define CASE_VECTOR_MODE SImode #define CASE_VECTOR_PC_RELATIVE (riscv_cmodel != CM_MEDLOW) diff --git a/gcc/config/riscv/thead.cc b/gcc/config/riscv/thead.cc index 20353995931..dc3aed3904d 100644 --- a/gcc/config/riscv/thead.cc +++ b/gcc/config/riscv/thead.cc @@ -883,6 +883,19 @@ th_output_move (rtx dest, rtx src) return NULL; } +/* Define ASM_OUTPUT_OPCODE to do anything special before + emitting an opcode. */ +const char * +th_asm_output_opcode (FILE *asm_out_file, const char *p) +{ + /* We need to add th. prefix to all the xtheadvector + instructions here.*/ + if (current_output_insn != NULL && p[0] == 'v') + fputs ("th.", asm_out_file); + + return p; +} + /* Implement TARGET_PRINT_OPERAND_ADDRESS for XTheadMemIdx. */ bool diff --git a/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c new file mode 100644 index 00000000000..eee727ef6b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/xtheadvector/prefix.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_xtheadvector -mabi=ilp32 -O0" } */ + +#include "riscv_vector.h" + +vint32m1_t +prefix (vint32m1_t vx, vint32m1_t vy, size_t vl) +{ + return __riscv_vadd_vv_i32m1 (vx, vy, vl); +} + +/* { dg-final { scan-assembler {\mth\.v\M} } } */ -- 2.17.1