This patch fixes SPEC2017 cam4 mismatch issue due to we miss has compatible
check
for conflict vsetvl fusion.
Buggy assembler before this patch:
.L69:
vsetvli a5,s1,e8,mf4,ta,ma -> buggy vsetvl
vsetivli zero,8,e8,mf2,ta,ma
vmv.v.i v1,0
vse8.v v1,0(a5)
j .L37
.L68:
vsetvli a5,s1,e8,mf4,ta,ma -> buggy vsetvl
vsetivli zero,8,e8,mf2,ta,ma
addi a3,a5,8
vmv.v.i v1,0
vse8.v v1,0(a5)
vse8.v v1,0(a3)
addi a4,a4,-16
li a3,8
bltu a4,a3,.L37
j .L69
.L67:
vsetivli zero,8,e8,mf2,ta,ma
vmv.v.i v1,0
vse8.v v1,0(a5)
addi a5,sp,56
vse8.v v1,0(a5)
addi s4,sp,64
addi a3,sp,72
vse8.v v1,0(s4)
vse8.v v1,0(a3)
addi a4,a4,-32
li a3,16
bltu a4,a3,.L36
j .L68
After this patch:
.L63:
ble s1,zero,.L49
slli a4,s1,3
li a3,32
addi a5,sp,48
bltu a4,a3,.L62
vsetivli zero,8,e8,mf2,ta,ma
vmv.v.i v1,0
vse8.v v1,0(a5)
addi a5,sp,56
vse8.v v1,0(a5)
addi s4,sp,64
addi a3,sp,72
vse8.v v1,0(s4)
addi a4,a4,-32
addi a5,sp,80
vse8.v v1,0(a3)
.L35:
li a3,16
bltu a4,a3,.L36
addi a3,a5,8
vmv.v.i v1,0
addi a4,a4,-16
vse8.v v1,0(a5)
addi a5,a5,16
vse8.v v1,0(a3)
.L36:
li a3,8
bltu a4,a3,.L37
vmv.v.i v1,0
vse8.v v1,0(a5)
Tested on both RV32/RV64 no regression, Ok for trunk ?
PR target/113429
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc: Fix bug of conflict vsetvl fusion.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/spec2017_cam4/ppgrid.mod: New test.
* gcc.target/riscv/rvv/spec2017_cam4/shr_kind_mod.mod: New test.
* gcc.target/riscv/rvv/spec2017_cam4/pr113429.f90: New test.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c: Adapt test.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c: Ditto.
---
gcc/config/riscv/riscv-vsetvl.cc | 39 ++++---
.../rvv/fortran/spec2017_cam4/ppgrid.mod | Bin 0 -> 296 bytes
.../rvv/fortran/spec2017_cam4/pr113429.f90 | 110 ++++++++++++++++++
.../fortran/spec2017_cam4/shr_kind_mod.mod | Bin 0 -> 499 bytes
.../gcc.target/riscv/rvv/rvv-fortran.exp | 2 +
.../riscv/rvv/vsetvl/vlmax_conflict-4.c | 5 +-
.../riscv/rvv/vsetvl/vlmax_conflict-5.c | 10 +-
7 files changed, 140 insertions(+), 26 deletions(-)
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/ppgrid.mod
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90
create mode 100644
gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/shr_kind_mod.mod
diff --git a/gcc/config/riscv/riscv-vsetvl.cc b/gcc/config/riscv/riscv-vsetvl.cc
index df7ed149388..76e3d2eb471 100644
--- a/gcc/config/riscv/riscv-vsetvl.cc
+++ b/gcc/config/riscv/riscv-vsetvl.cc
@@ -2254,6 +2254,22 @@ private:
return true;
}
+ bool has_compatible_reaching_vsetvl_p (vsetvl_info info)
+ {
+ unsigned int index;
+ sbitmap_iterator sbi;
+ EXECUTE_IF_SET_IN_BITMAP (m_vsetvl_def_in[info.get_bb ()->index ()], 0,
+ index, sbi)
+ {
+ const auto prev_info = *m_vsetvl_def_exprs[index];
+ if (!prev_info.valid_p ())
+ continue;
+ if (m_dem.compatible_p (prev_info, info))
+ return true;
+ }
+ return false;
+ }
+
bool preds_all_same_avl_and_ratio_p (const vsetvl_info &curr_info)
{
gcc_assert (
@@ -3075,22 +3091,8 @@ pre_vsetvl::earliest_fuse_vsetvl_info ()
{
vsetvl_info new_curr_info = curr_info;
new_curr_info.set_bb (crtl->ssa->bb (eg->dest));
- bool has_compatible_p = false;
- unsigned int def_expr_index;
- sbitmap_iterator sbi2;
- EXECUTE_IF_SET_IN_BITMAP (
- m_vsetvl_def_in[new_curr_info.get_bb ()->index ()], 0,
- def_expr_index, sbi2)
- {
- vsetvl_info &prev_info = *m_vsetvl_def_exprs[def_expr_index];
- if (!prev_info.valid_p ())
- continue;
- if (m_dem.compatible_p (prev_info, new_curr_info))
- {
- has_compatible_p = true;
- break;
- }
- }
+ bool has_compatible_p
+ = has_compatible_reaching_vsetvl_p (new_curr_info);
if (!has_compatible_p)
{
if (dump_file && (dump_flags & TDF_DETAILS))
@@ -3146,7 +3148,10 @@ pre_vsetvl::earliest_fuse_vsetvl_info ()
&& !m_dem.compatible_p (prev_info, curr_info))
{
/* Cancel lift up if probabilities are equal. */
- if (successors_probability_equal_p (eg->src))
+ if (successors_probability_equal_p (eg->src)
+ || (dest_block_info.probability
+ > src_block_info.probability
+ && !has_compatible_reaching_vsetvl_p (curr_info)))
{
if (dump_file && (dump_flags & TDF_DETAILS))
{
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/ppgrid.mod
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/ppgrid.mod
new file mode 100644
index
0000000000000000000000000000000000000000..cb021390ccd758e75c3ad11b33da93e5fba9dd25
GIT binary patch
literal 296
zcmV+@0oVQ?iwFP!000001J#p3PlGTRhVT6q@2zl{=@`s-tfVf)tq@kHSA}j8Hz3S;
z@Yh?$U?jR7j0cyt>GwAM+UHHbPVT~3#av=jq`S4ohpx6+k%JCBiloxd?>fb@DmEy~
zRh6Yz%d*TqwV7`iu`C;Z(McQF#DqT#2lPd+lGk1SMnM}A6Hp9cSqmNq{B|nvAn#@P
zC<lR5LaI(iap;qSfOv|gfgh;BoG%0zSaWloG7&M{ddaj_8>GE%0NIhX&LksHou~f}
z%QY-XvEF`Xig?UtLYWiJK(&GdvtL8`p`0sj4z|eo?bN0F=wJgq8=k>8<#-V;obgE;
u<HkmL89uI0`l$b5?-w#S{px2JbydgUwok|4b@my?Hu(ZO3A{OQ1ONc91&o{k
literal 0
HcmV?d00001
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90
new file mode 100644
index 00000000000..189735a0930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/pr113429.f90
@@ -0,0 +1,110 @@
+! { dg-do compile }
+! { dg-options "-march=rv64gcv -mabi=lp64d -Ofast -std=legacy" }
+
+module a
+ use shr_kind_mod, b => shr_kind_r8
+ use ppgrid
+
+ real(b) c
+ real(b) aa
+ real(b) ab
+
+ real(b) d
+ real(b) e
+contains
+subroutine f
+ real(b) g(pver)
+ real(b) ac(pver)
+ real(b) h(pver)
+ real(b) ad(pver)
+ real(b) ae(pver)
+ integer j(pcols)
+ integer l(pcols)
+ real(b) m(pver)
+ real(b) n(pver)
+ real(b) o(pver)
+ real(b) y(pver)
+ real(b) af(pver)
+ real(b) ag(pver)
+ real(b) ah(pver)
+ real(b) ai(pver)
+ real(b) aj(pcols)
+ real(b) r(pcols)
+ integer ak(pcols)
+ integer al(pcols)
+ real(b) am(pver)
+ real(b) an(pver)
+ real(b) ao(pver)
+ real(b) ap(pver)
+ real(b) aq(pver)
+ real(b) ar(pver)
+ real(b) as(pver)
+ real(b) at(pver)
+ real(b) au(pver)
+ real(b) av(pcols)
+ call aw(ax , m ,n ,o ,y ,af , ag ,as
,aq ,ar ,ao , ac ,g ,h ,an ,am , ap
,at ,ad ,ai ,ah , au ,ae ,av ,aj ,r , ak ,al
,j ,l ,1 , lengath ,d ,e ,aa ,c , ay ,ab )
+ call az(lengath )
+
+
+end
+subroutine aw(ax , q ,t ,p ,z ,s , ba ,as
,aq ,ar ,ao , ac ,g ,h ,an ,am ,
ap ,at ,ad ,bb ,u , bc ,ae ,av ,bd ,be ,
bf ,bg ,j ,bh ,il1g , il2g ,bi ,e ,bj ,c
, ay ,ab )
+ real(b) q(pver)
+ real(b) t(pver)
+ real(b) p(pver)
+ real(b) av(pcols)
+ real(b) z(pver)
+ real(b) s(pver)
+ real(b) ba(pver)
+ real(b) as(pver)
+ real(b) aq(pver)
+ real(b) ar(pver)
+ real(b) ao(pver)
+ real(b) ac(pver)
+ real(b) g(pver)
+ real(b) h(pver)
+ real(b) an(pver)
+ real(b) am(pver)
+ real(b) ap(pver)
+ real(b) at(pver)
+ real(b) ad(pver)
+ real(b) bb(pver)
+ real(b) u(1)
+ real(b) bc(pver)
+ real(b) bd(pcols)
+ real(b) be(pcols)
+ real(b) ae(pcols)
+ integer bf(pcols)
+ integer bg(pcols)
+ integer j(pcols)
+ integer bh(pcols)
+ real bk(pcols,pver)
+ real bl(pcols)
+ real(b) ab
+ real(b) bj
+ real(b) bm(pcols)
+ real(b) e
+ real(b) bi
+ real(b) c
+ do i = il1g,il2g
+ bl(i) = 2
+ end do
+ do k = 1,pver
+ do i = il1g,il1g
+ if (k <= v) then
+ w = bl(i)
+ bk = w
+ end if
+ end do
+ end do
+ bm(:il2g) = 0.
+ bn = minval(bg(:il2g))
+ do k = bn, bo
+ do i = il1g,il2g
+ if ( k <= 1) then
+ bm = bk(i,x)
+ endif
+ end do
+ av = bp(bm)
+ end do
+end
+end
diff --git
a/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/shr_kind_mod.mod
b/gcc/testsuite/gcc.target/riscv/rvv/fortran/spec2017_cam4/shr_kind_mod.mod
new file mode 100644
index
0000000000000000000000000000000000000000..b2d4df243182c9658d6fb4448d9f1949c8b71394
GIT binary patch
literal 499
zcmV<P0Sx{hiwFP!000001KpOvZlf>|hVOogxfu>w83HLeBH~u4iHRKOswcEcs1`LP
z6?9jtefk}o(ioTQq3WSTfb22G{y#i3_RV!7QyB_)I_!S!3;12sO?jw*IzEMMUHo_{
zcJNRio}l?z=Z|Hz%dzLThv(<=Z-M2U5zDgSGj7sVY=YH+#|7F7pg^s%da28*DYrIS
z6dbUuwM-(u$RvkM+=}G8n8YIGA_XjDEH-g8X}gfuw_Pt_cwJ{AO5;R8C}nt`Ct1p6
zzTj&v7F<O4M_ui3H(Y|JK4GM@QLt(`%6Csl*l3d}(5BcITl|kXs?I+^K>7smVFDs~
zxa{<UGWz1DhImgCkG`<~+Uh++y^rcUr`_(UW}yq8bcZrrah%Z9-I+br@oK${qd1*x
z!aJ^}8S)L#e1miXqeN`d5FPS=z0snsKclLyK;FVbG0k+QW;{#*8$iM!LZmAl>CbqO
ze8)YzOo2vGdgEd8&aTp2Ckn<x6r3e;n2uD92kHDGInFzXL8eu*$d>OC^&pUzrjJwU
zdAq$j`;?1`p{xxE$JM0N7ZDN8R7bjuknnV*iwKGK;MhL~Fz}5{l)=o{gBV;H8Js~t
p`WcYH+(;k{dO1b?GHi1U*JnmFsImIqbR5jH$v=xACV-#|004mu^f>?k
literal 0
HcmV?d00001
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
index a01c3d09170..8a54b7734c5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
+++ b/gcc/testsuite/gcc.target/riscv/rvv/rvv-fortran.exp
@@ -40,6 +40,8 @@ dg-init
# Main loop.
gfortran-dg-runtest [lsort \
[glob -nocomplain $srcdir/$subdir/fortran/*.\[fF\]{,90,95,03,08} ] ] "" ""
+gfortran-dg-runtest [lsort \
+ [glob -nocomplain
$srcdir/$subdir/fortran/spec2017_cam4/*.\[fF\]{,90,95,03,08} ] ] "" ""
# All done.
dg-finish
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
index 28ffe2c687a..dedbc94fb29 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-4.c
@@ -23,7 +23,6 @@ void f (int32_t * restrict in, int32_t * restrict out, size_t
n, size_t cond, si
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 3 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+\.L[0-9]:+} 1 {
target { no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 5 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
index cd94fdae4b4..26db192d836 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/vsetvl/vlmax_conflict-5.c
@@ -17,15 +17,13 @@ void f (int32_t * restrict in, int32_t * restrict out,
size_t n, size_t cond, si
vuint16mf2_t v = *(vuint16mf2_t*)(in + i + 300);
*(vuint16mf2_t*)(out + i + 300) = v;
} else {
- vbool1_t v = *(vbool1_t*)(in + i + 400);
- *(vbool1_t*)(out + i + 400) = v;
+ vint8mf8_t v = *(vint8mf8_t*)(in + i + 400);
+ *(vint8mf8_t*)(out + i + 400) = v;
}
}
}
/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e32,\s*mf2,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*m8,\s*t[au],\s*m[au]} 1 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
-/* { dg-final { scan-assembler-times {vsetvli} 4 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
+/* { dg-final { scan-assembler-times
{vsetvli\s+[a-x0-9]+,\s*zero,\s*e8,\s*mf8,\s*t[au],\s*m[au]} 2 { target {
no-opts "-O0" no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts
"-funroll-loops" no-opts "-g" } } } } */
+/* { dg-final { scan-assembler-times {vsetvli} 3 { target { no-opts "-O0"
no-opts "-O1" no-opts "-Os" no-opts "-Oz" no-opts "-funroll-loops" no-opts
"-g" } } } } */
--
2.36.3
