Hi,
on 2024/2/21 01:55, Carl Love wrote:
>
> GCC maintainers:
>
> This patch fixes the arguments and return type for the various
> __builtin_vsx_cmple* built-ins. They were defined as signed but should have
> been defined as unsigned.
>
> The patch has been tested on Power 10 with no regressions.
>
> Please let me know if this patch is acceptable for mainline. Thanks.
>
> Carl
>
> -----------------------------------------------------
>
> rs6000, Fix __builtin_vsx_cmple* args and documentation, builtins
>
> The built-ins __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u2di,
> __builtin_vsx_cmple_u4si and __builtin_vsx_cmple_u8hi should take
> unsigned arguments and return an unsigned result. This patch changes
> the arguments and return type from signed to unsigned.
Apparently the types mismatch the corresponding bif names, but I wonder
if these __builtin_vsx_cmple* actually provide some value?
Users can just use vec_cmple as PVIPR defines, as altivec.h shows,
vec_cmple gets redefined with vec_cmpge, these are not for the underlying
implementation. I also checked the documentation of openXL (xl compiler),
they don't support these either (these are not for compability).
So can we just remove these bifs?
>
> The documentation for the signed and unsigned versions of
> __builtin_vsx_cmple is missing from extend.texi. This patch adds the
> missing documentation.
>
> Test cases are added for each of the signed and unsigned built-ins.
>
> gcc/ChangeLog:
> * config/rs6000/rs6000-builtins.def (__builtin_vsx_cmple_u16qi,
> __builtin_vsx_cmple_u2di, __builtin_vsx_cmple_u4si): Change
> arguments and return from signed to unsigned.
> * doc/extend.texi (__builtin_vsx_cmple_16qi,
> __builtin_vsx_cmple_8hi, __builtin_vsx_cmple_4si,
> __builtin_vsx_cmple_u16qi, __builtin_vsx_cmple_u8hi,
> __builtin_vsx_cmple_u4si): Add documentation.
>
> gcc/testsuite/ChangeLog:
> * gcc.target/powerpc/vsx-cmple.c: New test file.
> ---
> gcc/config/rs6000/rs6000-builtins.def | 10 +-
> gcc/doc/extend.texi | 23 ++++
> gcc/testsuite/gcc.target/powerpc/vsx-cmple.c | 127 +++++++++++++++++++
> 3 files changed, 155 insertions(+), 5 deletions(-)
> create mode 100644 gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
>
> diff --git a/gcc/config/rs6000/rs6000-builtins.def
> b/gcc/config/rs6000/rs6000-builtins.def
> index 3bc7fed6956..d66a53a0fab 100644
> --- a/gcc/config/rs6000/rs6000-builtins.def
> +++ b/gcc/config/rs6000/rs6000-builtins.def
> @@ -1349,16 +1349,16 @@
> const vss __builtin_vsx_cmple_8hi (vss, vss);
> CMPLE_8HI vector_ngtv8hi {}
>
> - const vsc __builtin_vsx_cmple_u16qi (vsc, vsc);
> + const vuc __builtin_vsx_cmple_u16qi (vuc, vuc);
> CMPLE_U16QI vector_ngtuv16qi {}
>
> - const vsll __builtin_vsx_cmple_u2di (vsll, vsll);
> + const vull __builtin_vsx_cmple_u2di (vull, vull);
> CMPLE_U2DI vector_ngtuv2di {}
>
> - const vsi __builtin_vsx_cmple_u4si (vsi, vsi);
> + const vui __builtin_vsx_cmple_u4si (vui, vui);
> CMPLE_U4SI vector_ngtuv4si {}
>
> - const vss __builtin_vsx_cmple_u8hi (vss, vss);
> + const vus __builtin_vsx_cmple_u8hi (vus, vus);
> CMPLE_U8HI vector_ngtuv8hi {}
>
> const vd __builtin_vsx_concat_2df (double, double);
> @@ -1769,7 +1769,7 @@
> const vf __builtin_vsx_xvcvuxdsp (vull);
> XVCVUXDSP vsx_xvcvuxdsp {}
>
> - const vd __builtin_vsx_xvcvuxwdp (vsi);
> + const vd __builtin_vsx_xvcvuxwdp (vui);
> XVCVUXWDP vsx_xvcvuxwdp {}
This change is unexpected, it should not be in this sub-patch. :)
>
> const vf __builtin_vsx_xvcvuxwsp (vsi);
> diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi
> index 2b8ba1949bf..4d8610f6aa8 100644
> --- a/gcc/doc/extend.texi
> +++ b/gcc/doc/extend.texi
> @@ -22522,6 +22522,29 @@ if the VSX instruction set is available. The
> @samp{vec_vsx_ld} and
> @samp{vec_vsx_st} built-in functions always generate the VSX @samp{LXVD2X},
> @samp{LXVW4X}, @samp{STXVD2X}, and @samp{STXVW4X} instructions.
>
> +
> +@smallexample
> +vector signed char __builtin_vsx_cmple_16qi (vector signed char,
> + vector signed char);
> +vector signed short __builtin_vsx_cmple_8hi (vector signed short,
> + vector signed short);
> +vector signed int __builtin_vsx_cmple_4si (vector signed int,
> + vector signed int);
> +vector unsigned char __builtin_vsx_cmple_u16qi (vector unsigned char,
> + vector unsigned char);
> +vector unsigned short __builtin_vsx_cmple_u8hi (vector unsigned short,
> + vector unsigned short);
> +vector unsigned int __builtin_vsx_cmple_u4si (vector unsigned int,
> + vector unsigned int);
> +@end smallexample
We don't document any vsx_cmp*, that's why I thought they acts as internal
implementation for the external interfaces vec_cmp*, but as mentioned above
these eight (missing 2 DI, so 6 here) ones are useless.
BR,
Kewen
> +
> +The builti-ins @code{__builtin_vsx_cmple_16qi},
> @code{__builtin_vsx_cmple_8hi},
> +@code{__builtin_vsx_cmple_4si}, @code{__builtin_vsx_cmple_u16qi},
> +@code{__builtin_vsx_cmple_u8hi} and @code{__builtin_vsx_cmple_u4si} compare
> +vectors of their defined type. The corresponding result element is set to
> +all ones if the two argument elements are less than or equal and all zeros
> +otherwise.
> +
> @node PowerPC AltiVec Built-in Functions Available on ISA 2.07
> @subsubsection PowerPC AltiVec Built-in Functions Available on ISA 2.07
>
> diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> new file mode 100644
> index 00000000000..081817b4ba3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/powerpc/vsx-cmple.c
> @@ -0,0 +1,127 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target powerpc_altivec_ok } */
> +/* { dg-options "-maltivec -O2 -save-temps" } */
> +
> +#define DEBUG 0
> +
> +#include <altivec.h>
> +
> +#if DEBUG
> +#include <stdio.h>
> +#include <stdlib.h>
> +#endif
> +
> +void abort (void);
> +
> +#if DEBUG
> + #define ACTION(NAME, TYPE_NAME) \
> + printf ("test_vsx_cmple_%s: result_%s[%d] = 0x%x, expected_result_%s[%d] =
> 0x%x\n", \
> + #NAME, #TYPE_NAME, i, result_##TYPE_NAME[i], \
> + #TYPE_NAME, i, (int)expected_result_##TYPE_NAME[i]);
> +#else
> + #define ACTION(NAME, TYPE_NAME) \
> + abort();
> +#endif
> +
> +#define TEST(NAME, TYPE, TYPE_NAME) \
> +void test_vsx_cmple_##NAME (vector TYPE arg1_##TYPE_NAME, \
> + vector TYPE arg2_##TYPE_NAME, \
> + vector TYPE expected_result_##TYPE_NAME) \
> +{ \
> + vector TYPE result_##TYPE_NAME; \
> + int i, len = 16/sizeof(TYPE);
> \
> + \
> + result_##TYPE_NAME = __builtin_vsx_cmple_##NAME (arg1_##TYPE_NAME, \
> + arg2_##TYPE_NAME); \
> + for (i = 0; i < len; i++) \
> + if (result_##TYPE_NAME[i] != expected_result_##TYPE_NAME[i]) \
> + ACTION(TYPE, TYPE_NAME) \
> +}
> +
> +int main ()
> +{
> +
> + vector signed char vsc_arg1, vsc_arg2, vsc_expected_result;
> + vector signed short vsh_arg1, vsh_arg2, vsh_expected_result;
> + vector signed int vsi_arg1, vsi_arg2, vsi_expected_result;
> + vector signed long long vsll_arg1, vsll_arg2, vsll_expected_result;
> + vector unsigned char vuc_arg1, vuc_arg2, vuc_expected_result;
> + vector unsigned short vuh_arg1, vuh_arg2, vuh_expected_result;
> + vector unsigned int vui_arg1, vui_arg2, vui_expected_result;
> + vector unsigned long long vull_arg1, vull_arg2, vull_expected_result;
> +
> + vsc_arg1 = (vector signed char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
> + 14, 15, 16};
> + vsc_arg2 = (vector signed char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
> + 21, 22, 23, 24, 25, 26};
> + vsc_expected_result = (vector signed char) {0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF};
> + /* Test for __builtin_vsx_cmple_16qi */
> + TEST (16qi, signed char, vsc)
> + test_vsx_cmple_16qi (vsc_arg1, vsc_arg2, vsc_expected_result);
> +
> + vsh_arg1 = (vector signed short) {1, 2, 3, 4, 5, 6, 7, 8};
> + vsh_arg2 = (vector signed short) {11, 12, 13, 14, 15, 16, 17, 18};
> + vsh_expected_result = (vector signed short) {0xFFFF, 0xFFFF, 0xFFFF,
> 0xFFFF,
> + 0xFFFF, 0xFFFF, 0xFFFF, 0xFFFF};
> + /* Test for __builtin_vsx_cmple_8hi */
> + TEST (8hi, signed short, vsh)
> + test_vsx_cmple_8hi (vsh_arg1, vsh_arg2, vsh_expected_result);
> +
> + vsi_arg1 = (vector signed int) {1, 2, 3, 4};
> + vsi_arg2 = (vector signed int) {11, 12, 13, 14};
> + vsi_expected_result = (vector signed int) {0xFFFFFFFF, 0xFFFFFFFF,
> + 0xFFFFFFFF, 0xFFFFFFFF};
> + /* Test for __builtin_vsx_cmple_4si */
> + TEST (4si, signed int, vsi)
> + test_vsx_cmple_4si (vsi_arg1, vsi_arg2, vsi_expected_result);
> +
> + vsll_arg1 = (vector signed long long) {1, 2};
> + vsll_arg2 = (vector signed long long) {11, 12};
> + vsll_expected_result = (vector signed long long) {0xFFFFFFFFFFFFFFFF,
> + 0xFFFFFFFFFFFFFFFF};
> + /* Test for __builtin_vsx_cmple_2di */
> + TEST (2di, signed long long, vsll)
> + test_vsx_cmple_2di (vsll_arg1, vsll_arg2, vsll_expected_result);
> +
> + vuc_arg1 = (vector unsigned char) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
> 13,
> + 14, 15, 16};
> + vuc_arg2 = (vector unsigned char) {11, 12, 13, 14, 15, 16, 17, 18, 19, 20,
> 21,
> + 22, 23, 24, 25, 26};
> + vuc_expected_result = (vector unsigned char) {0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF,
> + 0xFF, 0xFF, 0xFF, 0xFF};
> + /* Test for __builtin_vsx_cmple_u16qi */
> + TEST (u16qi, unsigned char, vuc)
> + test_vsx_cmple_u16qi (vuc_arg1, vuc_arg2, vuc_expected_result);
> +
> + vuh_arg1 = (vector unsigned short) {1, 2, 3, 4, 5, 6, 7, 8};
> + vuh_arg2 = (vector unsigned short) {11, 12, 13, 14, 15, 16, 17, 18};
> + vuh_expected_result = (vector unsigned short) {0xFFFF, 0xFFFF,
> + 0xFFFF, 0xFFFF,
> + 0xFFFF, 0xFFFF,
> + 0xFFFF, 0xFFFF};
> + /* Test for __builtin_vsx_cmple_u8hi */
> + TEST (u8hi, unsigned short, vuh)
> + test_vsx_cmple_u8hi (vuh_arg1, vuh_arg2, vuh_expected_result);
> +
> + vui_arg1 = (vector unsigned int) {1, 2, 3, 4};
> + vui_arg2 = (vector unsigned int) {11, 12, 13, 14};
> + vui_expected_result = (vector unsigned int) {0xFFFFFFFF, 0xFFFFFFFF,
> + 0xFFFFFFFF, 0xFFFFFFFF};
> + /* Test for __builtin_vsx_cmple_u4si */
> + TEST (u4si, unsigned int, vui)
> + test_vsx_cmple_u4si (vui_arg1, vui_arg2, vui_expected_result);
> +
> + vull_arg1 = (vector unsigned long long) {1, 2};
> + vull_arg2 = (vector unsigned long long) {11, 12};
> + vull_expected_result = (vector unsigned long long) {0xFFFFFFFFFFFFFFFF,
> + 0xFFFFFFFFFFFFFFFF};
> + /* Test for __builtin_vsx_cmple_u2di */
> + TEST (u2di, unsigned long long, vull)
> + test_vsx_cmple_u2di (vull_arg1, vull_arg2, vull_expected_result);
> + return 0;
> +}
