Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern

钟居哲 Thu, 29 Feb 2024 23:24:10 -0800

Hello, han.&nbsp; Thanks for trying to optimize the codes.


But I believe those vector-scalar patterns (eq/ne) you remove in this patch are 
necessary.


This is the story:
1. For commutative RTL code in GCC like plus, eq, ne, ... etc,
&nbsp; &nbsp; we known in semantic Both (eq: (reg) (vec_duplicate ... ) and 
(eq: (vec_duplicate ...&nbsp;) (reg)) are right.
&nbsp; &nbsp; However, GCC prefer this order as I remembered - (eq: 
(vec_duplicate ...&nbsp;) (reg)).


2. Before this patch, the order of the comparison as follows (take eq and lt as 
an example):
&nbsp; &nbsp;&nbsp;
&nbsp; &nbsp; 1). (eq: (vec_duplicate ...&nbsp;) (reg))&nbsp; --&gt; commutative
&nbsp; &nbsp; 2). (lt: (reg) (vec_duplicate ... )&nbsp; &nbsp; &nbsp;--&gt; 
non-commutative
&nbsp; &nbsp;&nbsp;
&nbsp; &nbsp;These patterns order are different.
&nbsp; &nbsp;
&nbsp; &nbsp;So, you see we have dedicated patterns (seems duplicate patterns) 
for vector-scalar eq/ne, whereas, we unify eq/ne into other comparisons for 
vector-vector instructions.
&nbsp; &nbsp;If we unify eq/ne into other comparisons for vector-scalar 
instructions (like your patch does), we will end up have:
&nbsp; &nbsp;&nbsp;
&nbsp; &nbsp;(eq: (reg) (vec_duplicate ... ) [after this patch] instead of (eq: 
(vec_duplicate ...&nbsp;) (reg)) [Before this patch].


So, I think this patch may not be right.
I may be wrong, Robin/Jerff/kito feel free to correct me if I am wrong.
&nbsp;
&nbsp;
------------------&nbsp;Original&nbsp;------------------
From: &nbsp;"demin.han"<demin....@starfivetech.com&gt;;
Date: &nbsp;Fri, Mar 1, 2024 02:27 PM
To: &nbsp;"gcc-patches"<gcc-patches@gcc.gnu.org&gt;; 
Cc: &nbsp;"juzhe.zhong"<juzhe.zh...@rivai.ai&gt;; 
"kito.cheng"<kito.ch...@gmail.com&gt;; "Li, Pan2"<pan2...@intel.com&gt;; 
"jeffreyalaw"<jeffreya...@gmail.com&gt;; 
Subject: &nbsp;[PATCH 1/5] RISC-V: Remove float vector eqne pattern

&nbsp;

We can unify eqne and other comparison operations.

Tested on RV32 and RV64

gcc/ChangeLog:

        * config/riscv/riscv-vector-builtins-bases.cc: Remove eqne cond
        * config/riscv/vector.md (@pred_eqne<mode&gt;_scalar): Remove patterns
        (*pred_eqne<mode&gt;_scalar_merge_tie_mask): Ditto
        (*pred_eqne<mode&gt;_scalar): Ditto
        (*pred_eqne<mode&gt;_scalar_narrow): Ditto

Signed-off-by: demin.han <demin....@starfivetech.com&gt;
---
&nbsp;.../riscv/riscv-vector-builtins-bases.cc&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
|&nbsp; 4 -
&nbsp;gcc/config/riscv/vector.md&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 | 86 -------------------
&nbsp;2 files changed, 90 deletions(-)

diff --git a/gcc/config/riscv/riscv-vector-builtins-bases.cc 
b/gcc/config/riscv/riscv-vector-builtins-bases.cc
index b6f6e4ff37e..d414721ede8 100644
--- a/gcc/config/riscv/riscv-vector-builtins-bases.cc
+++ b/gcc/config/riscv/riscv-vector-builtins-bases.cc
@@ -1420,10 +1420,6 @@ public:
&nbsp;&nbsp;&nbsp;&nbsp; switch (e.op_info-&gt;op)
&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; {
&nbsp;  case OP_TYPE_vf: {
-       &nbsp; if (CODE == EQ || CODE == NE)
-       &nbsp;&nbsp;&nbsp; return e.use_compare_insn (CODE, 
code_for_pred_eqne_scalar (
-                                       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
e.vector_mode ()));
-       &nbsp; else
&nbsp;  &nbsp;&nbsp;&nbsp; return e.use_compare_insn (CODE, 
code_for_pred_cmp_scalar (
&nbsp;                                  &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
e.vector_mode ()));
&nbsp;  }
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index ab6e099852d..9210d7c28ad 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -7520,92 +7520,6 @@ (define_insn "*pred_cmp<mode&gt;_scalar_narrow"
&nbsp;&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
&nbsp;&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
&nbsp;
-(define_expand "@pred_eqne<mode&gt;_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 "register_operand")
-       (if_then_else:<VM&gt;
-       &nbsp; (unspec:<VM&gt;
-       &nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 "vector_mask_operand")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 "vector_length_operand")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 "const_int_operand")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 "const_int_operand")
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-       &nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-       &nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSF
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 
"register_operand"))
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSF 4 
"register_operand")])
-       &nbsp; (match_operand:<VM&gt; 2 "vector_merge_operand")))]
-&nbsp; "TARGET_VECTOR"
-&nbsp; {})
-
-(define_insn "*pred_eqne<mode&gt;_scalar_merge_tie_mask"
-&nbsp; [(set (match_operand:<VM&gt; 0 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "=vm")
-       (if_then_else:<VM&gt;
-       &nbsp; (unspec:<VM&gt;
-       &nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; 0")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 5 
"vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " rK")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 
"const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "&nbsp; i")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 
"const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "&nbsp; i")
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-       &nbsp; (match_operator:<VM&gt; 2 "equality_operator"
-       &nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSF
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 4 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp; f"))
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSF 3 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; " vr")])
-       &nbsp; (match_dup 1)))]
-&nbsp; "TARGET_VECTOR"
-&nbsp; "vmf%B2.vf\t%0,%3,%4,v0.t"
-&nbsp; [(set_attr "type" "vfcmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "merge_op_idx" "1")
-&nbsp;&nbsp; (set_attr "vl_op_idx" "5")
-&nbsp;&nbsp; (set (attr "ma") (symbol_ref "riscv_vector::get_ma(operands[6])"))
-&nbsp;&nbsp; (set (attr "avl_type_idx") (const_int 7))])
-
-;; We don't use early-clobber for LMUL <= 1 to get better codegen.
-(define_insn "*pred_eqne<mode&gt;_scalar"
-&nbsp; [(set (match_operand:<VM&gt; 0 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "=vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; &amp;vr,&nbsp;&nbsp; &amp;vr")
-       (if_then_else:<VM&gt;
-       &nbsp; (unspec:<VM&gt;
-       &nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 
"vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "vmWc1,vmWc1,vmWc1,vmWc1")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 
"vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
"&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 
"const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; 
i,&nbsp;&nbsp;&nbsp; i")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 
"const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; 
i,&nbsp;&nbsp;&nbsp; i")
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-       &nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-       &nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSF
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; 
f,&nbsp;&nbsp;&nbsp; f,&nbsp;&nbsp;&nbsp; f,&nbsp;&nbsp;&nbsp; f"))
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSF 4 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; vr,&nbsp;&nbsp; 
vr,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-       &nbsp; (match_operand:<VM&gt; 2 
"vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; 
vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_le_one (<MODE&gt;mode)"
-&nbsp; "vmf%B3.vf\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vfcmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "thv,thv,rvv,rvv")])
-
-;; We use early-clobber for source LMUL &gt; dest LMUL.
-(define_insn "*pred_eqne<mode&gt;_scalar_narrow"
-&nbsp; [(set (match_operand:<VM&gt; 0 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "=vm,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr,&nbsp; &amp;vr,&nbsp; &amp;vr")
-       (if_then_else:<VM&gt;
-       &nbsp; (unspec:<VM&gt;
-       &nbsp;&nbsp;&nbsp; [(match_operand:<VM&gt; 1 
"vector_mask_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; 
0,vmWc1,vmWc1,vmWc1,vmWc1")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 6 
"vector_length_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; 
"&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; rK,&nbsp;&nbsp; 
rK")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 7 
"const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; 
i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-       &nbsp;&nbsp;&nbsp;&nbsp; (match_operand 8 
"const_int_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;
 "&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; 
i,&nbsp;&nbsp;&nbsp; i,&nbsp;&nbsp;&nbsp; i")
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VL_REGNUM)
-       &nbsp;&nbsp;&nbsp;&nbsp; (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE)
-       &nbsp; (match_operator:<VM&gt; 3 "equality_operator"
-       &nbsp;&nbsp;&nbsp;&nbsp; [(vec_duplicate:V_VLSF
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:<VEL&gt; 5 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp;&nbsp; 
f,&nbsp;&nbsp;&nbsp; f,&nbsp;&nbsp;&nbsp; f,&nbsp;&nbsp;&nbsp; 
f,&nbsp;&nbsp;&nbsp; f"))
-       &nbsp;&nbsp;&nbsp;&nbsp;&nbsp; (match_operand:V_VLSF 4 
"register_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; 
vr,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vr,&nbsp;&nbsp; vr")])
-       &nbsp; (match_operand:<VM&gt; 2 
"vector_merge_operand"&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; "&nbsp;&nbsp; 
vu,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 0,&nbsp;&nbsp; vu,&nbsp;&nbsp;&nbsp; 
0")))]
-&nbsp; "TARGET_VECTOR &amp;&amp; riscv_vector::cmp_lmul_gt_one (<MODE&gt;mode)"
-&nbsp; "vmf%B3.vf\t%0,%4,%5%p1"
-&nbsp; [(set_attr "type" "vfcmp")
-&nbsp;&nbsp; (set_attr "mode" "<MODE&gt;")
-&nbsp;&nbsp; (set_attr "spec_restriction" "none,thv,thv,none,none")])
-
&nbsp;;; 
-------------------------------------------------------------------------------
&nbsp;;; ---- Predicated floating-point merge
&nbsp;;; 
-------------------------------------------------------------------------------
-- 
2.43.2

Re:[PATCH 1/5] RISC-V: Remove float vector eqne pattern

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