Hi,
Here is new version of patch based up on Paolo review, again tested on
arm-7l, mips-32r2 (74k), i686 without new regressions.
thanks, Dinar.On Sat, May 26, 2012 at 4:45 PM, Paolo Bonzini <bonz...@gnu.org> wrote: > Il 26/05/2012 14:35, Paolo Bonzini ha scritto: >> /* We have to return >> >> z2 + ((u0 + u1) >> GET_MODE_BITSIZE (word_mode)). >> >> u0 + u1 are the upper two words of the three-word >> intermediate result and they could have up to >> 2 * GET_MODE_BITSIZE (word_mode) + 1 bits of precision. >> We compute the extra bit by checking for carry, and add >> 1 << GET_MODE_BITSIZE (word_mode) to z2 if there is carry. */ > > Oops, GET_MODE_BITSIZE (word_mode) is more concisely BITS_PER_WORD. > >>> > + tmp = expand_binop (mode, add_optab, u0, u1, tmp, 1, >>> > OPTAB_LIB_WIDEN); >>> > + if (!tmp) >>> > + return 0; >> /* We have to return z2 + (tmp >> 32). We need >>> > + /* Checking for overflow. */ >> This is not overflow, it's carry (see above). >> >>> > + c = gen_reg_rtx (mode); >>> > + c1 = gen_reg_rtx (mode); >>> > + cres = gen_reg_rtx (mode); >>> > + >>> > + emit_store_flag_force (c, GT, u0, tmp, mode, 1, 1); >>> > + emit_store_flag_force (c1, GT, u1, tmp, mode, 1, 1); >>> > + result = expand_binop (mode, ior_optab, c, c1, cres, 1, >>> > OPTAB_LIB_WIDEN); >>> > + if (!result) >>> > + return 0; >>> > + >>> > + ccst = gen_reg_rtx (mode); >>> > + ccst = expand_shift (LSHIFT_EXPR, mode, cres, 32, ccst, 1); >> This 32 should be GET_MODE_BITSIZE (word_mode). > > Here, too. > > Paolo >
2012-06-07 Dinar Temirbulatov <dtemirbula...@gmail.com>
Alexey Kravets <mr.kayr...@gmail.com>
* config/arm/arm.c (arm_rtx_costs_1): Add cost estimate for the integer
double-word division operation.
* config/mips/mips.c (mips_rtx_costs): Extend cost estimate for the
integer
double-word division operation for 32-bit targets.
* gcc/expmed.c (expand_mult_highpart_optab): Allow to generate the
higher multipilcation
product for unsigned double-word integers using 32-bit wide registers.
28.patch
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